PS System Monitor Specifications

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

Document ID
DS926
Release Date
2024-05-31
Revision
1.13 English
Table 1. PS SYSMON Specifications
Parameter Comments Conditions Min Typ Max Units
VCC_PSADC = 1.8V ±3%, Tj = –40°C to 100°C, typical values at Tj = 40°C
ADC Accuracy (Tj = –55°C to 125°C) 1
Resolution 10 Bits
Sample rate 1 MS/s
RMS code noise On-chip reference 1 LSBs
On-Chip Sensor Accuracy
Temperature sensor error Tj = –55°C to 110°C ±3.5 °C
Tj = 110°C to 125°C ±5 °C
Supply sensor error 2 Supply voltages less than or electrically connected to VCC_PSADC Tj = –55°C to 125°C ±1 %
Supply voltages nominally at 1.8V but with the potential to go above VCC_PSADC Tj = –55°C to 125°C ±1.5 %
Supply voltages nominally in the 2.0V to 3.3V range Tj = –55°C to 125°C ±2.5 %
Conversion Rate 3
Conversion time—continuous tCONV Number of ADCCLK cycles 26 32 Cycles
Conversion time—event tCONV Number of ADCCLK cycles 21 Cycles
DRP clock frequency DCLK AMS REFCLK frequency 8 250 MHz
ADC clock frequency ADCCLK Derived from DCLK 1 26 MHz
  1. ADC offset errors are removed by enabling the ADC automatic offset calibration feature. The values are specified for when this feature is enabled.
  2. Supply sensor offset and gain errors are removed by enabling the automatic offset and gain calibration feature. The values are specified for when this feature is enabled.
  3. See the Adjusting the Acquisition Settling Time section in the UltraScale Architecture System Monitor User Guide (UG580).