PS Triple-timer Counter Interface

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

Document ID
DS926
Release Date
2024-05-31
Revision
1.13 English
Table 1. Triple-timer Counter Interface
Symbol Description Min Max Units
TPWTTCOCLK Triple-timer counter output clock pulse width 60.4 ns
FTTCOCLK Triple-timer counter output clock frequency 16.5 MHz
TTTCICLKL Triple-timer counter input clock high pulse width 1.5 x 1/FLPD_LSBUS_CTRLMAX ns
TTTCICLKH Triple-timer counter input clock low pulse width 1.5 x 1/FLPD_LSBUS_CTRLMAX ns
FTTCICLK Triple-timer counter input clock frequency FLPD_LSBUS_CTRLMAX/3 MHz
  1. All timing values assume an ideal external input clock. Your actual timing budget must account for additional external clock jitter.