Absolute Maximum Ratings - DS926

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)
Document ID
DS926
Release Date
2024-12-23
Revision
1.14 English
Table 1. Absolute Maximum Ratings
Symbol Description 1 Min Max Units

Processor System (PS)
VCC_PSINTFP PS primary logic full-power domain supply voltage –0.500 1.000 V
VCC_PSINTLP PS primary logic low-power domain supply voltage –0.500 1.000 V
VCC_PSAUX PS auxiliary supply voltage –0.500 2.000 V
VCC_PSINTFP_DDR PS DDR controller and PHY supply voltage –0.500 1.000 V
VCC_PSADC PS SYSMON ADC supply voltage relative to GND_PSADC –0.500 2.000 V
VCC_PSPLL PS PLL supply voltage –0.500 1.320 V
VPS_MGTRAVCC PS-GTR supply voltage –0.500 1.000 V
VPS_MGTRAVTT PS-GTR termination voltage –0.500 2.000 V
VPS_MGTREFCLK PS-GTR reference clock input voltage –0.500 1.100 V
VPS_MGTRIN PS-GTR receiver input voltage –0.500 1.100 V
VCCO_PSDDR PS DDR I/O supply voltage –0.500 1.650 V
VCC_PSDDR_PLL PS DDR PLL supply voltage –0.500 2.000 V
VCCO_PSIO PS I/O supply –0.500 3.630 V
VPSIN 2 PS I/O input voltage –0.500 VCCO_PSIO + 0.550 V
PS DDR I/O input voltage –0.500 VCCO_PSDDR + 0.550 V
VCC_PSBATT PS battery-backed RAM and battery-backed real-time clock (RTC) supply voltage –0.500 2.000 V

Programmable Logic (PL)
VCCINT Internal supply voltage –0.500 1.000 V
VCCINT_IO 3 Internal supply voltage for the I/O banks –0.500 1.000 V
VCCAUX 4 Auxiliary supply voltage –0.500 2.000 V
VCCBRAM 3 Supply voltage for the block RAM and UltraRAM –0.500 1.000 V
VCCO Output drivers supply voltage for HD I/O banks –0.500 3.400 V
Output drivers supply voltage for HP I/O banks –0.500 2.000 V
VCCAUX_IO 4 Auxiliary supply voltage for the I/O banks –0.500 2.000 V
VREF Input reference voltage for HP I/O banks –0.500 2.000 V
VIN 2, 5, 6 , 7 I/O input voltage for HD I/O banks –0.550 VCCO + 0.550 V
I/O input voltage for HP I/O banks –0.550 VCCO + 0.550 V
IDC Available output current at the pad –20 20 mA
IRMS Available RMS output current at the pad –20 20 mA

GTY Transceiver 8

VMGTAVCC Analog supply voltage for transceiver circuits –0.500 1.000 V
VMGTAVTT Analog supply voltage for transceiver termination circuits –0.500 1.300 V
VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for transceivers –0.500 1.900 V
VMGTREFCLK Transceiver reference clock absolute input voltage –0.500 1.300 V
VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the transceiver column –0.500 1.300 V
VIN Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage –0.500 1.200 V
IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating 9 – 10 mA
IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT – 10 mA
IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND 10 – 0 mA
IDCIN-PROG DC input current for receiver input pins DC coupled RX termination = programmable 11 – 0 mA
IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating – 6 mA
IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT – 6 mA

RF-ADC, RF-DAC, and SD-FEC
VADC_AVCC ADC and PLL supply voltage for ZU2xDR, ZU39DR, ZU4xDR –0.500 1.000 V
VADC_AVCC ADC and PLL supply voltage for ZU6xDR –0.500 1.110 V
VADC_AVCCAUX Input buffer and PLL supply voltage –0.500 2.000 V
VDAC_AVCC DAC and PLL supply voltage –0.500 1.000 V
VDAC_AVCCAUX Output buffer and PLL supply voltage –0.500 2.000 V
VDAC_AVTT DAC on-die 50Ω termination supply voltage –0.500 3.200 V
VCCINT_AMS Digital down converter supply voltage –0.500 1.000 V
VCCSDFEC SD-FEC supply voltage –0.500 1.000 V
VRFDC_CLK_IN ADC_CLK, DAC_CLK, and SYSREF input voltage –0.500 2.000 V
VADC_VIN 12 ADC_VIN input voltage for ZU2xDR and ZU39DR devices –0.300 2.100 V
ADC_VIN input voltage for ZU4xDR and ZU6xDR devices –0.500 2.100 V

PL System Monitor
VCCADC PL System Monitor supply relative to GNDADC –0.500 2.000 V
VREFP PL System Monitor reference input relative to GNDADC –0.500 2.000 V

Temperature 13

TSTG Storage temperature (ambient) –65 150 °C
TSOL Maximum dry rework soldering temperature – 260 °C
Maximum reflow soldering temperature for FFVD1156, FFVE1156, FSVE1156, FFVG1517, FSVG1517, FFVF1760, FSVF1760, FFVH1760, and FSVH1760 packages – 245 °C
Maximum reflow soldering temperature for FFRD1156, FFRE1156, FFRG1517, and FFRF1760 packages – 225 °C
Tj Maximum junction temperature – 125 °C
  1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
  2. When operating outside of the recommended operating conditions, refer to Table 1, Table 2, and Table 3 for maximum overshoot and undershoot specifications.
  3. VCCINT_IO must be connected to VCCBRAM.
  4. VCCAUX_IO must be connected to VCCAUX.
  5. The lower absolute voltage specification always applies.
  6. For I/O operation, see the UltraScale Architecture SelectIO Resources User Guide (UG571).
  7. VIN for the POR_OVERRIDE pin is unique. POR_OVERRIDE must be connected to either GND (default) or VCCINT. See TPOR in Configuration Switching Characteristics for additional information.
  8. For more information on supported GTY transceiver terminations see the UltraScale Architecture GTY Transceivers User Guide (UG578).
  9. AC coupled operation is not supported for RX termination = floating.
  10. For GTY transceivers, DC coupled operation is not supported for RX termination = GND.
  11. DC coupled operation is not supported for RX termination = programmable.
  12. The ADC maximum inputs are only valid when both ADC supplies are present. Do not apply input signals unless the ADC supplies are present.
  13. For soldering guidelines and thermal considerations, see the Zynq UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG1075).