PS-GTR Transceiver

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

Document ID
DS926
Release Date
2024-05-31
Revision
1.13 English
Table 1. PS-GTR Transceiver DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
DVPPIN Differential peak-to-peak input voltage (external AC coupled) 100 1200 mV
VIN Single-ended input voltage. Voltage measured at the pin referenced to GND 75 VPS_MGTRAVCC mV
VCMIN Common mode input voltage 0 mV
DVPPOUT Differential peak-to-peak output voltage 1 Transmitter output swing is set to maximum value 800 mV
VCMOUTAC Common mode output voltage: AC coupled (equation based) VPS_MGTRAVCC – DVPPOUT/2 mV
RIN Differential input resistance 100 Ω
ROUT Differential output resistance 100 Ω
RMGTRREF Resistor value between calibration resistor pin to GND 497.5 500 502.5 Ω
TOSKEW Transmitter output pair (TXP and TXN) intra-pair skew (All packages) 20 ps
CEXT Recommended external AC coupling capacitor 2 100 nF
  1. The output swing and pre-emphasis levels are programmable using the attributes discussed in the Zynq UltraScale+ Device Technical Reference Manual (UG1085), and can result in values lower than reported in this table.
  2. Other values can be used as appropriate to conform to specific protocols and standards.
Table 2. PS-GTR Transceiver Clock DC Input Level Specification
Symbol DC Parameter Min Typ Max Units
VIDIFF Differential peak-to-peak input voltage 250 2000 mV
RIN Differential input resistance 100 Ω
CEXT Required external AC coupling capacitor 10 nF
Table 3. PS-GTR Transceiver Performance
Symbol Description Speed Grade Units
-2 -1
FGTRMAX PS-GTR maximum line rate 6.0 6.0 Gb/s
FGTRMIN PS-GTR minimum line rate 1.25 1.25 Gb/s
Table 4. PS-GTR Transceiver PLL/Lock Time Adaptation
Symbol Description Min Typ Max Units
TLOCK Initial PLL lock 0.11 ms
TDLOCK Clock recovery phase acquisition and adaptation time 24 x 106 UI
Table 5. PS-GTR Transceiver Reference Clock Switching Characteristics
Symbol Description Conditions All Speed Grades Units
Min Typ Max
FGCLK Reference clock frequencies supported PCI Express® 1 100 MHz
SATA 125 MHz or 150 MHz
USB 3.0 26 MHz, 52 MHz, or 100 MHz
DisplayPort 27 MHz, 108 MHz, or 135 MHz
SGMII 125 MHz
TRCLK Reference clock rise time 20% – 80% 200 ps
TFCLK Reference clock fall time 80% – 20% 200 ps
TDCREF Reference clock duty cycle Transceiver PLL only 40 60 %
USB 3.0 with reference clock <40 MHz 47.5 52.5 %
  1. Only the common clock architecture is supported.
Table 6. PS-GTR Transceiver Reference Clock Oscillator Selection Phase Noise Mask
Symbol Description 1 Offset Frequency Min Typ Max Units
PLLREFCLKMASK PLL reference clock select phase noise mask at REFCLK frequency = 25 MHz 100 –102 dBc/Hz
1 KHz –124
10 KHz –132
100 KHz –139
1 MHz –152
10 MHz –154
PLL reference clock select phase noise mask at REFCLK frequency = 50 MHz 100 –96 dBc/Hz
1 KHz –118
10 KHz –126
100 KHz –133
1 MHz –146
10 MHz –148
PLL reference clock select phase noise mask at REFCLK frequency = 100 MHz 100 –90 dBc/Hz
1 KHz –112
10 KHz –120
100 KHz –127
1 MHz –140
10 MHz –142
PLL reference clock select phase noise mask at REFCLK frequency = 125 MHz 100 –88 dBc/Hz
1 KHz –110
10 KHz –118
100 KHz –125
1 MHz –138
10 MHz –140
PLL reference clock select phase noise mask at REFCLK frequency = 150 MHz 100 –86 dBc/Hz
1 KHz –108
10 KHz –116
100 KHz –123
1 MHz –136
10 MHz –138
  1. For reference clock frequencies not in this table, use the phase noise mask for the nearest reference clock frequency.
Table 7. PS-GTR Transceiver Transmitter Switching Characteristics
Symbol Description Condition Min Typ Max Units
FGTRTX Serial data rate range 1.25 6.0 Gb/s
TRTX TX rise time 20%–80% 65 ps
TFTX TX fall time 80%–20% 65 ps
Table 8. PS-GTR Transceiver Receiver Switching Characteristics
Symbol Description Condition Min Typ Max Units
FGTRRX Serial data rate 1.25 6 Gb/s
RXSST Receiver spread-spectrum tracking Modulated at 33 KHz –5000 0 ppm
RXPPMTOL Data/REFCLK PPM offset tolerance All data rates –350 350 ppm
Table 9. PCI Express Protocol Characteristics (PS-GTR Transceivers)
Standard Description 1 Line Rate (Mb/s) Min Max Units
PCI Express Transmitter Jitter Generation
PCI Express Gen 1 Total transmitter jitter 2500 0.25 UI
PCI Express Gen 2 Total transmitter jitter 5000 0.25 UI
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1 Total receiver jitter tolerance 2500 0.65 UI
PCI Express Gen 2 2 Receiver inherent timing error 5000 0.4 UI
Receiver inherent deterministic timing error 5000 0.3 UI
  1. Tested per card electromechanical (CEM) methodology.
  2. Between 1 MHz and 10 MHz the minimum sinusoidal jitter roll-off with a slope of 20 dB/decade.
Table 10. Serial ATA (SATA) Protocol Characteristics (PS-GTR Transceivers)
Standard Description Line Rate (Mb/s) Min Max Units
Serial ATA Transmitter Jitter Generation
SATA Gen 1 Total transmitter jitter 1500 0.37 UI
SATA Gen 2 Total transmitter jitter 3000 0.37 UI
SATA Gen 3 Total transmitter jitter 6000 0.52 UI
Serial ATA Receiver High Frequency Jitter Tolerance
SATA Gen 1 Total receiver jitter tolerance 1500 0.27 UI
SATA Gen 2 Total receiver jitter tolerance 3000 0.27 UI
SATA Gen 3 Total receiver jitter tolerance 6000 0.16 UI
Table 11. DisplayPort Protocol Characteristics (PS-GTR Transceivers)
Standard Description 1 Line Rate (Mb/s) Min Max Units
DisplayPort Transmitter Jitter Generation
RBR Total transmitter jitter 1620 0.42 UI
HBR Total transmitter jitter 2700 0.42 UI
HBR2 D10.2 Total transmitter jitter 5400 0.40 UI
HBR2 CPAT Total transmitter jitter 5400 0.58 UI
  1. Only the transmitter is supported.
Table 12. USB 3.0 Protocol Characteristics (PS-GTR Transceivers)
Standard Description Line Rate (Mb/s) Min Max Units
USB 3.0 Transmitter Jitter Generation
USB 3.0 Total transmitter jitter 5000 0.66 UI
USB 3.0 Receiver High Frequency Jitter Tolerance
USB 3.0 Total receiver jitter tolerance 5000 0.2 UI
Table 13. Serial-GMII Protocol Characteristics (PS-GTR Transceivers)
Standard Description Line Rate (Mb/s) Min Max Units
Serial-GMII Transmitter Jitter Generation
SGMII Deterministic transmitter jitter 1250 0.25 UI
Serial-GMII Receiver High Frequency Jitter Tolerance
SGMII Total receiver jitter tolerance 1250 0.25 UI