RF-ADC/RF-DAC to PL Interface Switching Characteristics

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

Document ID
DS926
Release Date
2024-05-31
Revision
1.13 English

The following table outlines the performance of the AXI4 interface.

Table 1. RF-ADC/RF-DAC to PL Interface Performance
Symbol Description 1 Min Max Units
FAXI_LITE_CLK AXI4-Lite clock frequency 10 250 MHz
FADC_GEARBOX_FIFO Maximum RF-ADC tile interface clock frequency for ZU25DR, ZU27DR, ZU28DR, ZU29DR, and ZU39DR 520 MHz
Maximum RF-ADC tile interface clock frequency for ZU42DR, ZU43DR, ZU46DR, ZU47DR, ZU48DR, ZU49DR, ZU63DR, ZU64DR, ZU65DR, and ZU67DR 614 MHz
FDAC_GEARBOX_FIFO Maximum RF-DAC tile interface clock frequency for ZU25DR, ZU27DR, ZU28DR, ZU29DR, and ZU39DR 500 MHz
Maximum RF-DAC tile interface clock frequency for ZU42DR, ZU43DR, ZU46DR, ZU47DR, ZU48DR, ZU49DR, ZU63DR, ZU64DR, ZU65DR, and ZU67DR with digital up converter (DUC) enabled 614 MHz
Maximum RF-DAC tile interface clock frequency for ZU42DR, ZU43DR, ZU46DR, ZU47DR, ZU48DR, ZU49DR, ZU63DR, ZU64DR, ZU65DR, and ZU67DR with DUC bypassed 625 MHz
  1. See the Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) for information on the AXI4-Stream clock frequencies needed to achieve data transfer for specific DAC and ADC interface settings.