Recommended Operating Conditions

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

Document ID
DS926
Release Date
2024-05-31
Revision
1.13 English
Table 1. Recommended Operating Conditions
Symbol Description 1, 2 Min Typ Max Units

Processor System

VCC_PSINTFP 3 PS full-power domain supply voltage 0.808 0.850 0.892 V
For -1LI, -2LI, and -2LE (VCCINT = 0.72V) devices: PS full-power domain supply voltage 0.808 0.850 0.892 V
VCC_PSINTLP PS low-power domain supply voltage 0.808 0.850 0.892 V
For -1LI, -2LI, and -2LE (VCCINT = 0.72V) devices: PS low-power domain supply voltage 0.808 0.850 0.892 V
VCC_PSAUX PS auxiliary supply voltage 1.710 1.800 1.890 V
VCC_PSINTFP_DDR 3 PS DDR controller and PHY supply voltage 0.808 0.850 0.892 V
For -1LI, -2LI, and -2LE (VCCINT = 0.72V) devices: PS DDR controller and PHY supply voltage 0.808 0.850 0.892 V
VCC_PSADC PS SYSMON ADC supply voltage relative to GND_PSADC 1.710 1.800 1.890 V
VCC_PSPLL PS PLL supply voltage 1.164 1.200 1.236 V
VPS_MGTRAVCC 4 PS-GTR supply voltage 0.825 0.850 0.875 V
VPS_MGTRAVTT 4 PS-GTR termination voltage 1.746 1.800 1.854 V
VCCO_PSDDR 5 PS DDR I/O supply voltage 1.06 1.575 V
VCC_PSDDR_PLL PS DDR PLL supply voltage 1.710 1.800 1.890 V
VCCO_PSIO 6 PS I/O supply 1.710 3.465 V
VPSIN PS I/O input voltage –0.200

VCCO_PSIO + 0.200

V
PS DDR I/O input voltage –0.200

VCCO_PSDDR + 0.200

V
VCC_PSBATT 7 PS battery-backed RAM and battery-backed real-time clock (RTC) supply voltage 1.200 1.500 V

Programmable Logic

VCCINT

PL internal supply voltage

0.825 0.850 0.876 V

For -1LI, -2LI, and -2LE (VCCINT = 0.72V) devices: PL internal supply voltage

0.698 0.720 0.742 V
VCCINT_IO 8

PL internal supply voltage for the I/O banks

0.825 0.850 0.876 V

For -1LI, -2LI, and -2LE (VCCINT = 0.72V) devices: PL internal supply voltage for the I/O banks

0.825 0.850 0.876 V
VCCBRAM Block RAM and UltraRAM supply voltage 0.825 0.850 0.876 V
VCCAUX Auxiliary supply voltage 1.746 1.800 1.854 V
VCCO Supply voltage for HD I/O banks 9 1.140 3.400 V
Supply voltage for HP I/O banks and configuration bank 0 10 0.950 1.900 V
VCCAUX_IO 11 Auxiliary I/O supply voltage 1.746 1.800 1.854 V
VIN 12, 13 I/O input voltage –0.200 VCCO + 0.200 V
IIN 14

Maximum current through any PL or PS pin in a powered or unpowered bank when forward biasing the clamp diode

10 mA

GTY Transceiver

VMGTAVCC 15

Analog supply voltage for the GTY transceiver

0.873 0.900 0.927 V
VMGTAVTT 15

Analog supply voltage for the GTY transmitter and receiver termination circuits

1.164 1.200 1.236 V
VMGTVCCAUX 15

Auxiliary analog QPLL voltage supply for the transceivers

1.746 1.800 1.854 V
VMGTAVTTRCAL 15

Analog supply voltage for the resistor calibration circuit of the GTY transceiver column

1.164 1.200 1.236 V

RF-ADC, RF-DAC, and SD-FEC

VADC_AVCC ADC and PLL supply voltage for ZU2xDR, ZU39DR, ZU4xDR 0.897 0.925 0.953 V
VADC_AVCC ADC and PLL supply voltage for ZU6xDR 0.980 1.010 1.040 V
VADC_AVCCAUX Input buffer and PLL supply voltage 1.746 1.800 1.854 V
VDAC_AVCC DAC and PLL supply voltage 0.897 0.925 0.953 V
VDAC_AVCCAUX Output buffer and PLL supply voltage 1.746 1.800 1.854 V
VDAC_AVTT 16 Termination voltage, on-die 50Ω termination resistors: 20 mA 2.425 2.500 2.575 V
Termination voltage, on-die 50Ω termination resistors: 32 mA 2.910 3.000 3.090 V
Termination voltage, on-die 50Ω termination resistors variable output power (VOP) disabled 17 2.425 2.500 2.575 V
Termination voltage, on-die 50Ω termination resistors VOP enabled 17 2.910 3.000 3.090 V
VCCINT_AMS 18 Digital down converter supply voltage 0.825 0.850 0.876 V
VCCSDFEC 19 SD-FEC supply voltage 0.825 0.850 0.876 V

PL System Monitor

VCCADC

PL System Monitor supply relative to GNDADC

1.746 1.800 1.854 V
VREFP

PL System Monitor externally supplied reference voltage relative to GNDADC

1.200 1.250 1.300 V

Temperature

Tj 20 Junction temperature operating range for extended (E) temperature devices 21 0 100 °C
Junction temperature operating range for industrial (I) temperature devices 22 –40 100 °C
Junction temperature operating range for military (M) temperature devices –55 125 °C
Junction temperature operating range for eFUSE programming –40 125 °C
  1. All voltages are relative to GND, assuming supplies are present.
  2. For the design of the power distribution system consult the UltraScale Architecture PCB Design User Guide (UG583).
  3. VCC_PSINTFP_DDR must be tied to VCC_PSINTFP.
  4. Each voltage listed requires filtering as described in the UltraScale Architecture PCB Design User Guide (UG583).
  5. Includes VCCO_PSDDR of 1.2V, 1.35V, 1.5V at ±5% and 1.1V +0.07V/–0.04V depending upon the tolerances required by specific memory standards.
  6. Applies to all PS I/O supply banks. Includes VCCO_PSIO of 1.8V, 2.5V, and 3.3V at ±5%.
  7. Up to 1.89V is acceptable on VCC_PSBATT. If the battery-backed RAM or RTC is not used, connect VCC_PSBATT to GND or VCC_PSAUX.
  8. VCCINT_IO must be connected to VCCBRAM.
  9. Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, and 2.5V at ±5%, and 3.3V at +3/–5%.
  10. Includes VCCO of 1.0V, 1.2V, 1.35V, 1.5V, and 1.8V at ±5%.
  11. VCCAUX_IO must be connected to VCCAUX.
  12. The lower absolute voltage specification always applies.
  13. VIN for the POR_OVERRIDE pin is unique. POR_OVERRIDE must be connected to either GND (default) or VCCINT. See TPOR in Configuration Switching Characteristics for additional information.
  14. A total of 200 mA per bank should not be exceeded.
  15. Each voltage listed requires filtering as described in the UltraScale Architecture GTY Transceivers User Guide (UG578) .
  16. RF-DAC output current swing must be set to 32 mA for 3V termination when using ZU2xDR or ZU39DR devices.
  17. When using the VOP feature and DC coupling mode, VOP range is reduced. See RF-DAC Electrical Characteristics for supported output power range.
  18. AMD recommends connecting VCCINT_AMS to VCCBRAM.
  19. VCCSDFEC must be connected to VCCBRAM.
  20. AMD recommends measuring the Tj of a device using the system monitor as described in the UltraScale Architecture System Monitor User Guide (UG580). The SYSMON temperature measurement errors (that are described in Table 1 and Table 1) must be accounted for in your design. For example, when using the PL system monitor with an external reference of 1.25V, and when SYSMON reports 97°C, there is a measurement error ±3°C. A reading of 97°C is considered the maximum adjusted Tj (100°C – 3°C = 97°C).
  21. Devices labeled with the speed/temperature grade of -2LE can operate for a limited time at a junction temperature between 100°C and 110°C. Timing parameters adhere to the same speed file at 110°C as they do below 110°C, regardless of operating voltage (nominal voltage of 0.85V or a low-voltage of 0.72V). Operation up to Tj = 110°C is limited to 1% of the device lifetime and can occur sequentially or at regular intervals as long as the total time does not exceed 1% of the device lifetime.
  22. Devices labeled with the speed/temperature grade of -2LI can operate for a limited time at a junction temperature between 100°C and 110°C. Timing parameters adhere to the same speed file at 110°C as they do below 110°C. Operation up to Tj = 110°C is limited to 5% of the device lifetime and can occur sequentially or at regular intervals as long as the total time does not exceed 5% of the device lifetime.