Programmable Logic (PL) Performance Characteristics

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

Document ID
DS926
Release Date
2024-05-31
Revision
1.13 English

This section provides the performance characteristics of some common functions and designs implemented in the Zynq UltraScale+ RFSoCs. These values are subject to the same guidelines as the AC Switching Characteristics section.

In each of the following LVDS performance tables, the I/O bank type is either high performance (HP) or high density (HD).

In LVDS component mode:

  • For the input/output registers in HP I/O banks, the Vivado tools limit clock frequencies to 312.9 MHz for all speed grades.
  • For IDDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades.
  • For ODDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades.
Table 1. LVDS Component Mode Performance
Description I/O Bank Type Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
Min Max Min Max Min Max Min Max
LVDS TX DDR (OSERDES 4:1, 8:1) HP 0 1250 0 1250 0 1250 0 1250 Mb/s
LVDS TX SDR (OSERDES 2:1, 4:1) HP 0 625 0 625 0 625 0 625 Mb/s
LVDS RX DDR (ISERDES 1:4, 1:8) 1 HP 0 1250 0 1250 0 1250 0 1250 Mb/s
LVDS RX DDR HD 0 250 0 250 0 250 0 250 Mb/s
LVDS RX SDR (ISERDES 1:2, 1:4) 1 HP 0 625 0 625 0 625 0 625 Mb/s
LVDS RX SDR HD 0 125 0 125 0 125 0 125 Mb/s
  1. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and should be removed through PCB routing.
Table 2. LVDS Native Mode Performance
Description 1, 2 DATA_WIDTH I/O Bank Type Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2E/-2I/-2LE -1E/-1I/

-1M/-1LI

-2LE -2LI -1LI
Min Max Min Max Min Max Min Max Min Max
LVDS TX DDR (TX_BITSLICE) 4 HP 375 1600 375 1600 375 1400 375 1260 375 1260 Mb/s
8 375 1600 375 1600 375 1600 375 1600 375 1600 Mb/s
LVDS TX SDR (TX_BITSLICE) 4 HP 187.5 800 187.5 800 187.5 700 187.5 630 187.5 630 Mb/s
8 187.5 800 187.5 800 187.5 800 187.5 800 187.5 800 Mb/s
LVDS RX DDR (RX_BITSLICE) 3 4 HP 375 1600 4 375 1600 4 375 1400 4 375 1260 4 375 1260 4 Mb/s
8 375 1600 4 375 1600 4 375 1600 4 375 1600 4 375 1600 4 Mb/s
LVDS RX SDR (RX_BITSLICE) 3 4 HP 187.5 800 187.5 800 187.5 700 187.5 630 187.5 630 Mb/s
8 187.5 800 187.5 800 187.5 800 187.5 800 187.5 800 Mb/s
  1. Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite. The performance values assume a source-synchronous interface.
  2. PLL settings can restrict the minimum allowable data rate. For example, when using the PLL with CLKOUTPHY_MODE = VCO_HALF the minimum frequency is PLL_FVCOMIN/2.
  3. LVDS receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and should be removed through PCB routing.
  4. Asynchronous receiver performance is limited to 1300 Mb/s for the -2E, -2I, and -2LE speed grades and to 1250 Mb/s for the -2LI, -1E, -1I, -1M, and -1LI speed grades.
Table 3. MIPI D-PHY Performance
Description I/O Bank Type Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -2 -1
MIPI D-PHY transmitter or receiver HP 1500 1 1260 2 1260 2 1260 Mb/s
  1. The Zynq UltraScale+ RFSoCs performance is specified at 1500 Mb/s when designing with Vivado Design Suite v2019.1 or earlier. For XC devices, the performance is specified at 2500 Mb/s when designing with Vivado Design Suite v2019.1.1 or later. XQ devices are specified at 1500 Mb/s specification.
  2. The Zynq UltraScale+ RFSoCs performance is specified at 1260 Mb/s when designing with Vivado Design Suite v2019.1 or earlier. For XC devices, the performance is specified at 2500 Mb/s when designing with Vivado Design Suite v2019.1.1 or later. XQ devices are specified at 1260 Mb/s.
Table 4. LVDS Native-Mode 1000BASE-X Support
Description 1 I/O Bank Type Speed Grade and VCCINT Operating Voltages
0.85V 0.72V
-2 -1 -2 -1
1000BASE-X HP Yes
  1. 1000BASE-X support is based on the IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications (IEEE Std 802.3-2008).

The following table provides the maximum data rates for applicable memory standards using the Zynq UltraScale+ RFSoC memory PHY. Refer to Memory Solutions for the complete list of memory interface standards supported and detailed specifications. The final performance of the memory interface is determined through a complete design implemented in the Vivado Design Suite, following guidelines in the UltraScale Architecture PCB Design User Guide (UG583), electrical analysis, and characterization of the system.

Table 5. Maximum Physical Interface (PHY) Rate for Memory Interfaces
Memory Standard DRAM Type Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2E/-2I/-2LE -1E/-1I/-1M/-1LI -2LE -2LI -1LI
DDR4 Single rank component 2666 2400 2400 2400 2133 Mb/s
1 rank DIMM 1, 2, 3 2400 2133 2133 2133 1866 Mb/s
2 rank DIMM 1, 4 2133 1866 1866 1866 1600 Mb/s
4 rank DIMM 1, 5 1600 1333 1333 1333 N/A Mb/s
DDR3 Single rank component 2133 2133 2133 1866 1866 Mb/s
1 rank DIMM 1, 2 1866 1866 1866 1600 1600 Mb/s
2 rank DIMM 1, 4 1600 1600 1600 1333 1333 Mb/s
4 rank DIMM 1, 5 1066 1066 1066 800 800 Mb/s
DDR3L Single rank component 1866 1866 1866 1600 1600 Mb/s
1 rank DIMM 1, 2 1600 1600 1600 1333 1333 Mb/s
2 rank DIMM 1, 4 1333 1333 1333 1066 1066 Mb/s
4 rank DIMM 1, 5 800 800 800 606 606 Mb/s
QDR II+ Single rank component 6 633 600 600 550 550 MHz
RLDRAM 3 Single rank component 1200 1066 1066 933 933 MHz
QDR IV XP Single rank component 1066 1066 933 933 933 MHz
LPDDR3 Single rank component 1600 1600 1600 1600 1600 Mb/s
  1. Dual in-line memory module (DIMM) includes RDIMM, SODIMM, UDIMM, and LRDIMM.
  2. Includes: 1 rank 1 slot, DDP 2 rank, LRDIMM 2 or 4 rank 1 slot.
  3. For the DDR4 DDP components at -2 (VCCINT = 0.85V) speed grade, the maximum data rate is 2133 Mb/s for six or more DDP devices. For five or less DDP devices, use the single rank DIMM data rates for the -2 (VCCINT = 0.85V) speed grade.
  4. Includes: 2 rank 1 slot, 1 rank 2 slot, LRDIMM 2 rank 2 slot.
  5. Includes: 2 rank 2 slot, 4 rank 1 slot.
  6. The QDRII+ performance specifications are for burst-length 4 (BL = 4) implementations.