RF Converters Clocking Characteristics

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

Document ID
DS926
Release Date
2024-05-31
Revision
1.13 English
Table 1. RF Converters Clocking Characteristics for ZU2xDR Devices
Symbols Parameter Comments/Conditions Min Typ 1 Max Units
FIN Tile clock input frequency range FREF range restrictions apply when the PLL is used. The FS range restriction applies when PLL is bypassed. 102.40625 6554 MHz
R 2 Frequency input division ratio

Possible values are 1, 2, 3, 4

Only available when using internal PLL

1 1 1  
FREF Reference input frequency

FREF = FIN/R

On-chip PLL activated 102.40625 615 MHz
FS Input sampling frequency PLL bypassed, quad ADC tile configuration 500 2058 MHz
PLL bypassed, dual ADC tile configuration 1000 4096 MHz
PLL bypassed, DAC 500 6554 MHz
VIN Input clock range 3 Into 100Ω differential, on-die termination 0.9 1.8 VPPD
RODT Input resistance

On-die differential termination 4

95 100 110 Ω
α Input duty cycle 48 52 %
FOUT FPLL output PLL output frequency range 5 500 6554 MHz
Sync Channel to channel synchronized delay skew Using multi-tile synchronization (MTS) feature on a single device –1 0 1 1/FS
PN 6 Phase noise 7 Offset = 100 kHz –127 –121.2 dBc/Hz
Offset = 1 MHz –130 –127.3 dBc/Hz
Offset = 2.5 MHz –136 –132.6 dBc/Hz
Offset = 10 MHz –146 –142.7 dBc/Hz
RS 8 Reference spur –70 dBc
RHS 8 Reference harmonic spur Offset from carrier ˂800 MHz –70 dBc
Offset from carrier >800 MHz –80 dBc
  1. Typical values are specified at nominal voltage, Tj = 40°C.
  2. Only R=1 is characterized.
  3. Maximum input voltage peak-to-peak is VADC_AVCCAUX. Only AC coupling mode is supported for this input.
  4. See the S parameter file information for more details on input characteristics.
  5. The internal PLL uses an integer reference divider (R), an integer feedback divider, and an integer output divider for enhanced oscillator performance on the output range.
  6. Phase noise specification applies for a reference frequency of 245.760 MHz using a division ratio = 1 and sufficient jitter performance of the reference (equal or better than Crystek Microwave's CRBSCS-01-245.760).
  7. Normalized to 1 GHz carrier.
  8. Assuming same reference frequency is used in all RF-DACs/RF-ADCs. Reference spurs levels are normalized to 1 GHz carrier. Reference spurs are found at FOUT ± N x FREF, where N = 1 for RS and N is an integer greater than 1 for RHS.
Table 2. RF Converters Clocking Characteristics for ZU39DR Devices
Symbols Parameter Comments/Conditions Min Typ 1 Max Units
FIN Tile clock input frequency range FREF range restrictions apply when the PLL is used. The FS range restriction applies when PLL is bypassed. 102.40625 6554 MHz
R 2 Frequency input division ratio

Possible values are 1, 2, 3, 4

Only available when using internal PLL

1 1 1  
FREF Reference input frequency

FREF = FIN/R

On-chip PLL activated 102.40625 615 MHz
FS Input sampling frequency PLL bypassed, quad ADC tile configuration 500 2220 MHz
PLL bypassed, DAC 500 6554 MHz
VIN Input clock range 3 Into 100Ω differential, on-die termination 0.9 1.8 VPPD
α Input duty cycle 48 52 %
FOUT FPLL output PLL output frequency range 4 500 6554 MHz
Sync Channel to channel synchronized delay skew Using multi-tile synchronization (MTS) feature on a single device –1 0 1 1/FS
PN 5 Phase noise 6 Offset = 100 kHz –127 –121.2 dBc/Hz
Offset = 1 MHz –130 –127.3 dBc/Hz
Offset = 2.5 MHz –136 –132.6 dBc/Hz
Offset = 10 MHz –146 –142.7 dBc/Hz
RS 7 Reference spur –70 dBc
RHS 7 Reference harmonic spur Offset from carrier ˂800 MHz –70 dBc
Offset from carrier >800 MHz –80 dBc
  1. Typical values are specified at nominal voltage, Tj = 40°C.
  2. Only R=1 is characterized.
  3. Maximum input voltage peak-to-peak is VADC_AVCCAUX. Only AC coupling mode is supported for this input.
  4. The internal PLL uses an integer reference divider (R), an integer feedback divider, and an integer output divider for enhanced oscillator performance on the output range.
  5. Phase noise specification applies for a reference frequency of 245.760 MHz using a division ratio = 1 and sufficient jitter performance of the reference (equal or better than Crystek Microwave's CRBSCS-01-245.760).
  6. Normalized to 1 GHz carrier.
  7. Assuming same reference frequency is used in all RF-DACs/RF-ADCs. Reference spurs levels are normalized to 1 GHz carrier. Reference spurs are found at FOUT ± N x FREF, where N = 1 for RS and N is an integer greater than 1 for RHS.
Table 3. RF Converters Clocking Characteristics for ZU4xDR Devices
Symbols Parameter Comments/Conditions Min Typ 1 Max Units
FIN 2 Tile clock input frequency range FREF range restrictions apply when the PLL is used. The FS range restriction applies when PLL is bypassed. 102.40625 10000 MHz
R 3 Frequency input division ratio

Possible values are 1, 2, 3, 4

Only available when using internal PLL

1 1 1  
FREF Reference input frequency

FREF = FIN/R

On-chip PLL activated 102.40625 615 MHz
FS Input sampling frequency PLL bypassed, quad ADC tile configuration 500 2500 MHz
PLL bypassed, dual ADC tile configuration 500 5000 MHz
PLL bypassed, DAC 500 10000 MHz
VIN Input clock range 4 Into 100Ω differential, on-die termination 0.9 2.8 VPPD
α Input duty cycle 48 52 %
SR Input clock slew rate 4 V/ns
FOUT FPLL output RF-ADC PLL output frequency range 5 500 5000 MHz
RF-DAC PLL output Low frequency range 5 500 6882 MHz
RF-DAC PLL output High frequency range 5 7863 10000 MHz
Sync Channel to channel synchronized delay skew Using multi-tile synchronization (MTS) feature on a single device –1 0 1 1/FS
RX Sync 6 Channel to channel synchronized delay skew for RFADC tile group in single device Using MTS feature and clock forwarding from center tiles of the ADC group with either external T1 clock or single RF-PLL output T1 clock –10 0 10 ps
TX Sync 6 Channel to channel synchronized delay skew for RFADC tile group in single device Using MTS feature and clock forwarding from center tiles of the DAC group with either external T1 clock or single RF-PLL output T1 clock –10 0 10 ps
PN_ADC 7 Phase noise for the RF-ADC 8 Offset = 100 kHz –127.0 –124.1 dBc/Hz
Offset = 1 MHz –130.7 –128.1 dBc/Hz
Offset = 2.5 MHz –136.0 –135.3 dBc/Hz
Offset = 10 MHz –148.1 –143.2 dBc/Hz
PN_DAC 7 Phase noise for the RF-DAC 8 Offset = 100 kHz –126.0 –121.7 dBc/Hz
Offset = 1 MHz –130.7 –128.0 dBc/Hz
Offset = 2.5 MHz –135.8 –135.3 dBc/Hz
Offset = 10 MHz –147.3 –144.2 dBc/Hz
RS 9 Reference spur –70 dBc
RHS 9 Reference harmonic spur Offset from carrier ˂800 MHz –70 dBc
Offset from carrier >800 MHz –80 dBc
  1. Typical values are specified at nominal voltage, Tj = 40°C.
  2. External full-rate clocking assumes best case achievable P to N skew from an external clock source. Consult the UltraScale Architecture PCB Design User Guide (UG583) for information on the impact of DAC maximum sample rate and external clocking skew imbalance.
  3. Only R=1 is characterized.
  4. The input clock should not be applied before the VDAC_AVCCAUX supply or the VADC_AVCCAUX supply is applied. Only AC coupling mode is supported for this input.
  5. The internal PLL uses an integer reference divider (R), an integer feedback divider, and an integer output divider for enhanced oscillator performance on the output range. The internal PLL does not supply a carrier between the Low and High frequency range of the DAC tile.
  6. The sampling clock can be sourced either from the on-chip RF-PLL or using direct external access from the selected center tile that is sourcing the group.
  7. Phase noise specification applies for a reference frequency of 245.760 MHz using a division ratio = 1 and sufficient jitter performance of the reference (equal or better than the Rohde and Schwarz SMB100A: RF continuous wave generator).
  8. Normalized to 1 GHz carrier.
  9. Assuming same reference frequency is used in all RF-DACs/RF-ADCs. Reference spurs levels are normalized to 1 GHz carrier. Reference spurs are found at FOUT ± N x FREF, where N = 1 for RS and N is an integer greater than 1 for RHS. The specification is derated by 3 dB when distributing a reference frequency to multiple PLLs.
Table 4. RF Converters Clocking Characteristics for ZU6xDR Devices
Symbols Parameter Comments/Conditions Min Typ 1 Max Units
FIN 2 Tile clock input frequency range FREF range restrictions apply when the PLL is used. The FS range restriction applies when PLL is bypassed. 102.40625 10000 MHz
R 3 Frequency input division ratio

Possible values are 1, 2, 3, 4

Only available when using internal PLL

1 1 1  
FREF Reference input frequency

FREF = FIN/R

On-chip PLL activated 102.40625 615 MHz
FS Input sampling frequency PLL bypassed, quad ADC tile configuration 500 2950 MHz
PLL bypassed, dual ADC tile configuration 500 5900 MHz
PLL bypassed, DAC 500 10000 MHz
VIN Input clock range 4 Into 100Ω differential, on-die termination 0.9 2.8 VPPD
α Input duty cycle 48 52 %
SR Input clock slew rate 4 V/ns
FOUT FPLL output RF-ADC PLL output frequency range 5 500 5900 MHz
RF-DAC PLL output Low frequency range 5 500 6882 MHz
RF-DAC PLL output High frequency range 5 7863 10000 MHz
Sync Channel to channel synchronized delay skew Using multi-tile synchronization (MTS) feature on a single device –1 0 1 1/FS
RX Sync 6 Channel to channel synchronized delay skew for RFADC tile group in single device Using MTS feature and clock forwarding from tile 1 (of tiles 0, 1, 2) of the ADC group with either external T1 clock or single RF-PLL output T1 clock –10 0 10 ps
TX Sync 6 Channel to channel synchronized delay skew for RFADC tile group in single device Using MTS feature and clock forwarding from tile 1 (of tiles 0, 1) of the DAC group with either external T1 clock or single RF-PLL output T1 clock –10 0 10 ps
PN_ADC 7 Phase noise for the RF-ADC 8 Offset = 100 kHz –127.0 –124.1 dBc/Hz
Offset = 1 MHz –130.7 –128.1 dBc/Hz
Offset = 2.5 MHz –136.0 –135.3 dBc/Hz
Offset = 10 MHz –148.1 –143.2 dBc/Hz
PN_DAC 7 Phase noise for the RF-DAC 8 Offset = 100 kHz –126.0 –121.7 dBc/Hz
Offset = 1 MHz –130.7 –128.0 dBc/Hz
Offset = 2.5 MHz –135.8 –135.3 dBc/Hz
Offset = 10 MHz –147.3 –144.2 dBc/Hz
RS 9 Reference spur –70 dBc
RHS 9 Reference harmonic spur Offset from carrier ˂800 MHz –70 dBc
Offset from carrier >800 MHz –80 dBc
  1. Typical values are specified at nominal voltage, Tj = 40°C.
  2. External full-rate clocking assumes best case achievable P to N skew from an external clock source. Consult the UltraScale Architecture PCB Design User Guide (UG583) for information on the impact of DAC maximum sample rate and external clocking skew imbalance.
  3. Only R=1 is characterized.
  4. The input clock should not be applied before the VDAC_AVCCAUX supply or the VADC_AVCCAUX supply is applied. Only AC coupling mode is supported for this input.
  5. The internal PLL uses an integer reference divider (R), an integer feedback divider, and an integer output divider for enhanced oscillator performance on the output range. The internal PLL does not supply a carrier between the Low and High frequency range of the DAC tile.
  6. The sampling clock can be sourced either from the on-chip RF-PLL or using direct external access.
  7. Phase noise specification applies for a reference frequency of 245.760 MHz using a division ratio = 1 and sufficient jitter performance of the reference (equal or better than the Rohde and Schwarz SMB100A: RF continuous wave generator).
  8. Normalized to 1 GHz carrier.
  9. Assuming same reference frequency is used in all RF-DACs/RF-ADCs. Reference spurs levels are normalized to 1 GHz carrier. Reference spurs are found at FOUT ± N x FREF, where N = 1 for RS and N is an integer greater than 1 for RHS. The specification is derated by 3 dB when distributing a reference frequency to multiple PLLs.
Table 5. Analog_SYSREF Clocking Characteristics
Symbol Parameter Comments/Conditions Min Typ Max Units
VIN Input range Into 100Ω differential, on-die termination 0.4 3.6 VPPD
Jitter SYSREF jitter RMS jitter from 100 Hz to 20 MHz 1 ps
FSYSREF SYSREF frequency   0.4 10 MHz
Slew rate Input clock slew rate 20% to 80% 2 V/ns
Pulse width Input clock pulse width   50 ns
DC Coupling Input Parameters
VIH Input High   0.2 1.8 V
VCM Common mode   0.1 1.7 V
VIL Input Low   0 1.6 V