PS SPI Controller Interface

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)

Document ID
DS926
Release Date
2024-05-31
Revision
1.13 English
Table 1. SPI Interfaces
Symbol Description 1 Min Max Units
SPI Master Interface
TDCMSPICLK SPI master mode clock duty cycle 45 55 %
TMSPISSSCLK Slave select asserted to first active clock edge 1 2 FSPI_REF_CLK cycles
TMSPISCLKSS Last active clock edge to slave select deasserted 1 2 FSPI_REF_CLK cycles
TMSPIDCK Input setup time for MISO –2.0 ns
TMSPICKD Input hold time for MISO 0.3 FMSPICLK cycles
TMSPICKO MOSI and slave select clock to out delay –2.0 5.0 ns
FMSPICLK SPI master device clock frequency 50 MHz
FSPI_REF_CLK SPI reference clock frequency 200 MHz
SPI Slave Interface
TSSPISSSCLK Slave select asserted to first active clock edge 2 FSPI_REF_CLK cycles
TSSPISCLKSS Last active clock edge to slave select deasserted 2 FSPI_REF_CLK cycles
TSSPIDCK Input setup time for MOSI 5.0 ns
TSSPICKD Input hold time for MOSI 1 FSPI_REF_CLK cycles
TSSPICKO MISO clock to out delay 0.0 13.0 ns
FSSPICLK SPI slave mode device clock frequency 25 MHz
FSPI_REF_CLK SPI reference clock frequency 200 MHz
  1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a 30 pF load.
  2. Valid when two SPI_REF_CLK delays are programmed between CS and CLK for TMSPISSSCLK, and between CLK and CS for TMSPISCLKSS in the SPI delay_reg0 register.