The PCIe DMA Tab is shown in the following figure.
Figure 1. PCIe DMA Tab
- Descriptor Bypass for Read/Write (H2C/C2H)
- Two options to select from.Note: In this mode (Internal mode) DMA will not bypass any H2C or C2H descriptors.
- Descriptor bypass and Internal
- In this mode descriptor ports for bypass out and bypass in are both enabled. Based on the context settings H2C or C2H descriptors can be sent out on descriptor bypass out. User can send in descriptors on Descriptor bypass in ports.
- C2H Stream Completion
-
- C2H Stream Completion Color bits
- Completion Color bit position in completion
entry. There are seven registers available to program, from bit
0 to 511 (for 64 bytes completion). You can program the bits,
and generate a BIT file. During the DMA transfer, the input pins
s_axis_c2h_cmpt_ctrl_color_idx[2:0]
determine which Color bit position to use. Default bit position 1 is selected in register 0.
- C2H Stream Completion Error bits
- Completion Error bit position in completion
entry. There are seven registers available to program, from bit
0 to 511 (for 64 bytes completion). You can program the bits,
and generate a BIT file. During a DMA transfer, the input pins
s_axis_c2h_cmpt_ctrl_err_idx[2:0]
determine which Error bit position to use. Default bit position 2 is selected in register 0.
- Performance options
-
- Pre-fetch cache depth
- The Prefetch cache supports up to 64 Queues. Select one of 16 or 64 (default 16). The Prefetch cache can support that many active queues at any given time. When one active queue finishes fetch and delivers all the descriptors for the packets of that queue, it then releases cache entry for other active queues. A larger cache size supports more active queues, but the area will also increase.
- Data Protection
- Parity Checking and end to end data protection. By default, data protection
is not enabled.
When Data Protection is not enabled:
- You do not need to give any CRC/ECC values on C2H data and the control interface.
- This will not log any Error and will not drop any packet.
- User should ground the ECC and CRC ports.
- CMPT parity check is not affected by this parameter. Note: You must always give the parity on CMPT.