IP Facts - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

Document ID
PG302
Release Date
2022-05-20
Version
4.0 English
LogiCORE IP Facts Table
Subsystem Specifics
Supported Device Family 1 UltraScale+™
Supported User Interfaces AXI4 Memory Map, AXI4-Stream, AXI4-Lite
Resources Resource Use web page.
Subsystem
Design Files Encrypted System Verilog
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx® Constraints File (XDC)
Simulation Model Verilog
Supported S/W Driver Linux, DPDK, and Windows Drivers 2
Tested Design Flows 3
Design Entry Vivado Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 70927
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. For driver details, see Xilinx DMA IP Drivers.
  3. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.
  4. For Versal ACAP, refer to Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344).