The slave bridge monitors AXI read and write burst type inputs to
ensure that only the INCR (incrementing burst) type is requested. Any other value on
these inputs is treated as an error condition and the Slave Illegal Burst (SIB)
interrupt is asserted. In the case of a read request, the Bridge asserts SLVERR for
all data beats and arbitrary data is placed on the s_axi_rdata
bus. In the case of a write request, the Bridge asserts SLVERR for the
write response and all write data is discarded.