Port Descriptions - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

Document ID
PG302
Release Date
2022-05-20
Version
4.0 English

The QDMA Subsystem for PCIe connects directly to the PCIe Integrated Block. The datapath interfaces to the PCIe Integrated Block IP are 64, 128, 256 or 512-bits wide, and runs at up to 250 MHz depending on the configuration of the IP. The datapath width applies to all data interfaces. Ports associated with this core are described below.

Table 1. Parameters
Parameter Name Description
PL_LINK_CAP_MAX_LINK_WIDTH Phy lane width
C_M_AXI_ADDR_WIDTH AXI4 Master interface Address width
C_M_AXI_ID_WIDTH AXI4 Master interface id width
C_M_AXI_DATA_WIDTH

AXI4 Master interface data width

64 or 128 or 256 or 512 bits

C_S_AXI_ID_WIDTH AXI4 Bridge Slave interface id width
C_S_AXI_ADDR_WIDTH AXI4 Bridge Slave interface Address width
C_S_AXI_DATA_WIDTH

AXI4 Bridge Slave interface data width

64 or 128 or 256 or 512 bits

C_S_AXI_ID_WIDTH AXI4 Bridge Slave interface id width
AXI_DATA_WIDTH

AXI4 DMA transfer data width.

Example 64 or 128 or 256 or 512 bits