AXI Memory Mapped Example Design - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

Document ID
Release Date
4.0 English
Figure 1. AXI Memory Map Example Design

The example design above is generated when the DMA Interface Selection option is set to AXI-MM only in the Basic tab. In this mode, the AXI MM interface is connected to a 512 KB block RAM. The diagram above shows that AXI4-Lite Master is connected to a 4 KB block RAM. For Host to Card (H2C) transfers, the DMA reads data from the Host and writes to the block RAM. For Card to Host (C2H) transfers, the DMA reads data from the block RAM and writes to the Host memory.