The following table shows the revision history for this document.
Section | Revision Summary |
---|---|
05/20/2022 Version 4.0 | |
Slave Bridge | Updated BDF table. |
AXI4-Lite Master Ports | Updated Config AXI4-Lite Memory Mapped Read Master Interface Port Descriptions table. |
AXI4-Stream C2H Ports | Updated AXI4-Stream C2H Port Descriptions table. |
Tandem Configuration | Updated for new device support. |
Dynamic Function eXchange over PCIe | Added new section. |
Debug Guide | Added new section. |
01/05/2022 Version 4.0 | |
General updates | Updated PDF keywords. |
12/17/2021 Version 4.0 | |
QDMA Global Ports | Added csr_prog_done. |
Queue Status Ports | Updated marker_cookie port. |
04/15/2021 Version 4.0 | |
Slave Bridge | Added more details regarding BDF tables and address translation, with examples provided. |
Tandem Configuration, and Basic Tab | Added information about for Dynamic Function eXchange (DFX) over PCIe support. |
07/01/2020 Version 4.0 | |
C2H Stream Packet Type | Updated Marker response for QDMA 4.0 (from Queues Status ports rather than descriptor bypass out ports). |
Host Profile | Added a new Host Profile Context table that needs to be programmed. |
Register Space | Updated the register CSV files. Updated the register address. Added tip to expose all debug registers. |
06/10/2020 Version 4.0 | |
Register Space | Reorganized section. Some register were updated. |
QDMA_CSR (0x0000) and Bridge Register Space | Moved register descriptions to CSV file external to product guide. |
Descriptor Context and Completion Context Structure | Updated some context tables. |
Context Programming | Added a new Host Profile Context table that needs to be programmed. |
Port Descriptions | Removed ports, and added new ports. |
Customizing and Generating the Subsystem | Updated options and descriptions for Vivado 2020.1. |
PCIe BARs Tab | Increased QDMA bar size to 256Kbytes in PFs, and 32Kbytes in VFs. |
Debug and Additional Options Tab | Added. |
Upgrading | Added reference to AR for changes between core versions. |
11/22/2019 Version 3.0 | |
RTL Version Register (0x22414) | Added PF RTL version register in the doc |
RTL Version Register (0x5014) | Added VF RTL version register in the doc |
AXI4-Stream Status Ports | Added the axis_c2h_status_error port. This port will be available starting in a 2019.2 patch release. |
QDMA C2H Descriptor Bypass Output Marker Response Descriptions table | Added C2H Stream marker_cookie field for marker response. This feature will be available starting in a 2019.2 patch release. |
QDNA_GLBL2_MISC_CAP (0x134) | Updated available bits and descriptions. |
VDM | Added information regarding back-to-back VDM access not being supported. |
05/22/2019 Version 3.0 | |
Performance and Resource Utilization | Added performance details, and Performance Report answer record. |
Minimum Device Requirements | Enabled Gen4 devices for QDMA. |
User Parameters | Added link to AR for additional core customization options. |
Capabilities Tab | Mailbox can be selected independently of SR-IOV selection. |
AXI Stream Loopback Example Design | New example design added. |
12/05/2018 Version 3.0 | |
IP Facts and Using the Drivers | Added Windows driver support. |
Register Space | Added registers, and updated registers. |
PCIe MISC Tab and PCIe DMA Tab | Updated for the 2018.3 release. |
Example Design | Added two example designs, and updated registers. |
Upgrading | Added reference to AR for changes between core versions. |
09/04/2018 Version 2.0 | |
Port Descriptions | For tm_dsc_sts_rdy (VDM Ports) and st_rx_msg_rdy (QDMA Traffic Manager Credit Output Ports), emphasized that when this interface is not used, Ready must be tied-off to 1. |
Register Space | Added a register to stall read requests from H2C Stream Engine if the amount of outstanding data exceeds a programmed threshold. |
Added a new C2H Completion interrupt trigger mode that includes user trigger, timer expiration, or count exceeding the threshold | |
06/22/2018 Version 2.0 | |
Overview chapter |
Updated content throughout. |
Port Descriptions section | Changed some table content, and some reorganization of the content. |
Register Space section | Added Memory Map Register Space and AXI4-Lite Slave Register Space section. |
Context Structure Definition section, and Queue Entry Structure section | Removed these sections, and moved content into the QDMA Operations section in the Overview chapter. |
Design Flow Steps chapter | Updated descriptions for Basic Tab, Capabilities Tab, PCIe BARs Tab, PCIe Misc Tab, and PCIe DMA Tab. |
Example Design chapter | Added two new example designs, and added example design registers. |
04/17/2018 Version 1.0 | |
Initial Xilinx release. |