AXI Memory Mapped Bridge Master Interface - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)
Document ID
PG302
Release Date
2022-05-20
Version
4.0 English

The AXI MM Bridge Master interface is used for high bandwidth access to AXI Memory Mapped space from the host. The interface supports up to 32 outstanding AXI reads and writes. One or more PCIe BAR of any physical function (PF) or virtual function (VF) can be mapped to the AXI-MM bridge master interface. This selection must be made prior to design compilation. The function ID, BAR ID, VF group, and VF group offset will be made available as part of aruser and awuser of the AXI-MM interface allowing the user logic to identify the source of each memory access. The m_axib_awuser/m_axib_aruser[54:0] user bits mapping is listed in AXI Bridge Master Ports.

Virtual function group (VFG) refers to the VF group number. It is equivalent to the PF number associated with the corresponding VF. VFG_OFFSET refers to the VF number with respect to a particular PF. Note that this is not the FIRST_VF_OFFSET of each PF.

For example, if both PF0 and PF1 have 8 VFs, FIRST_VF_OFFSET for PF0 and PF1 is 4 and 11. Below is the mapping for VFG and VFG_OFFSET.

Table 1. AXI-MM Interface Virtual Function Group
Function Number PF Number VFG VFG_OFFSET
0 0 0 0
1 1 0 0
4 0 0 0 (Because FIRST_VF_OFFSET for PF0 is 4, the first VF of PF0 starts at FN_NUM=4 and VFG_OFFSET=0 indicates this is the first VF for PF0)
5 0 0 1 (VFG_OFFSET=1 indicates this is the second VF for PF0)
... ... ... ...
12 1 1 0 (VFG=1 indicates this VF is associated with PF1)
13 1 1 1

Each host initiated access can be uniquely mapped to the 64-bit AXI address space through the PCIe to AXI BAR translation.

Since all functions share the same AXI Master address space, a mechanism is needed to map requests from different functions to a distinct address space on the AXI master side. An example provided below shows how PCIe to AXI translation vector is used. Note that all VFs belonging to the same PF share the same PCIe to AXI translation vector. Therefore, the AXI address space of each VF is concatenated together. Use VFG_OFFSET to calculate the actual starting address of AXI for a particular VF.

To summarize, m_axib_awaddr is determined as:

  • For PF, m_axib_awaddr = pcie2axi_vec + axib_offset.
  • For VF, m_axib_awaddr = pcie2axi_vec + (VFG_OFFSET + 1)*vf_bar_size + axib_offset.

Where pcie2axi_vec is PCIe to AXI BAR translation (that can be set when the IP core is configured from the Vivado® IP catalog).

And axib_offset is the address offset in the requested target space.