C2H_CONTROL_REG (0x008) - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

Document ID
PG302
Release Date
2022-05-20
Version
4.0 English
Table 1. C2H_CONTROL_REG (0x008)
Bit Default Access Type Description
[31:6] 0 NA Reserved
[5] 0 RW C2H Stream Marker request

C2H Stream Marker response will be registered at address 0x18, bit [0].

[4] 0 NA reserved
[3] 0 RW Disable completion. For this packet, there will not be any completion.
[2] 0 RW Immediate data.

When set, the data generator sends immediate data. This is a self-clearing bit. Write 1 to initiate transfer.

[1] 0 RW Starts AXI-ST C2H transfer. This is a self-clearing bit. Write 1 to initiate transfer.
[0] 0 RW Streaming loop back. When set, the data packet from H2C streaming port in the Card side is looped back to the C2H streaming ports.

For Normal C2H stream packet transfer, set address offset 0x08 to 0x2.

For C2H immediate data transfer, set address offset 0x8 to 0x4.

For C2H/H2C stream loopback, set address offset 0x8 to 0x1.