AXI Bridge Master Ports - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

Document ID
PG302
Release Date
2022-05-20
Version
4.0 English
Table 1. AXI4 Memory Mapped Master Bridge Read Address Interface Port Descriptions
Signal Name I/O Description
m_axib_araddr

[C_M_AXI_ADDR_WIDTH-1:0]

O This signal is the address for a memory mapped read to the user logic from the host.
m_axib_arid

[C_M_AXI_ID_WIDTH-1:0]

O Master read address ID.
m_axib_arlen[7:0] O Master read address length.
m_axib_arsize[2:0] O Master read address size.
m_axib_arprot[2:0] O Master read protection type.
m_axib_arvalid O The assertion of this signal means there is a valid read request to the address on m_axib_araddr.
m_axib_arready I Master read address ready.
m_axib_arlock O Master read lock type.
m_axib_arcache[3:0] O Master read memory type.
m_axib_arburst[1:0] O Master read address burst type.
m_axib_aruser[28:0] O Master read user bits.

m_axib_aruser[10:0] = reserved

m_axib_aruser[11] = bridge traffic

m_axib_aruser[15:12] = bar id

m_axib_aruser[18:16] = reserved

m_axib_aruser[30:19] = function number

m_axib_aruser[31] = reserved

m_axib_aruser[39:32] = bus number

m_axib_aruser[42:40] = vf group

m_axib_aruser[54:43] = vfg offset

Table 2. AXI4 Memory Mapped Master Bridge Read Interface Port Descriptions
Signal Name I/O Description
m_axib_rdata

[C_M_AXI_DATA_WIDTH-1:0]

I Master read data.
m_axib_ruser

[C_M_AXI_DATA_WIDTH/8-1:0]

I m_axib_ruser[C_M_DATA_WIDTH/8-1:0] = read data odd parity, per byte.
m_axib_rid

[C_M_AXI_ID_WIDTH-1:0]

I Master read ID.
m_axib_rresp[1:0] I Master read response.
m_axib_rlast I Master read last.
m_axib_rvalid I Master read valid.
m_axib_rready O Master read ready.
Table 3. AXI4 Memory Mapped Master Bridge Write Address Interface Port Descriptions
Signal Name I/O Description
m_axib_awaddr

[C_M_AXI_ADDR_WIDTH-1:0]

O This signal is the address for a memory mapped write to the user logic from the host.
m_axib_awid

[C_M_AXI_ID_WIDTH-1:0]

O Master write address ID.
m_axib_awlen[7:0] O Master write address length.
m_axib_awsize[2:0] O Master write address size.
m_axib_awburst[1:0] O Master write address burst type.
m_axib_awprot[2:0] O Master write protection type.
m_axib_awvalid O The assertion of this signal means there is a valid write request to the address on m_axib_araddr.
m_axib_awready I Master write address ready.
m_axib_awlock O Master write lock type.
m_axib_awcache[3:0] O Master write memory type.
m_axib_awuser[28:0] O Master write user bits.

m_axib_aruser[10:0] = reserved

m_axib_aruser[11] = bridge traffic

m_axib_aruser[15:12] = bar id

m_axib_aruser[18:16] = reserved

m_axib_aruser[30:19] = function number

m_axib_aruser[31] = reserved

m_axib_aruser[39:32] = bus number

m_axib_aruser[42:40] = vf group

m_axib_aruser[54:43] = vfg offset

Table 4. AXI4 Memory Mapped Master Bridge Write Interface Port Descriptions
Signal Name I/O Description
m_axib_wdata

[C_M_AXI_DATA_WIDTH-1:0]

O Master write data.
m_axib_wuser

[C_M_AXI_DATA_WIDTH/8-1:0]

O

m_axib_wuser

[C_M_AXI_DATA_WIDTH/8-1:0] = write data odd parity, per byte.
m_axib_wlast O Master write last.
m_axib_wstrb

[C_M_AXI_DATA_WIDTH/8-1:0]

O Master write strobe.
m_axib_wvalid O Master write valid.
m_axib_wready I Master write ready.
Table 5. AXI4 Memory Mapped Master Bridge Write Response Interface Port Descriptions
Signal Name I/O Description
m_axib_bvalid I Master write response valid.
m_axib_bresp[1:0] I Master write response.
m_axib_bid

[C_M_AXI_ID_WIDTH-1:0]

I Master write response ID.
m_axib_bready O Master response ready.