User Interrupts - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

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4.0 English
Table 1. User Interrupts Port Descriptions
Port Name I/O Description
usr_irq_in_vld I Valid

An assertion indicates that an interrupt associated with the vector, function, and pending fields on the bus should be generated to PCIe. Once asserted, Usr_irq_in_vld must remain high until usr_irq_out_ack is asserted by the DMA.

usr_irq_in_vec [11:0] I Vector

The MSIX vector to be sent.

Vector starts from 0 to 7. Vector 0 is the first vector.

usr_irq_in_fnc [7:0] I Function

The function of the vector to be sent.

usr_irq_out_ack O Interrupt Acknowledge

An assertion of the acknowledge bit indicates that the interrupt was transmitted on the link the user logic must wait for this pulse before signaling another interrupt condition.

usr_irq_out_fail O Interrupt Fail

An assertion of fail indicates that the interrupt request was aborted before transmission on the link.

Eight vectors is the maximum allowed per function.