Basic Tab - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

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4.0 English

The Basic tab is shown in the following figure.

Figure 1. Basic Tab

Functional Mode
Option to select between QDMA and AXI Bridge.
Allows you to select the Basic or Advanced mode of the configuration of core.
Device /Port Type
Only PCI Express® Endpoint device mode is supported.
GT Selection/Enable GT Quad Selection
Select the Quad in which lane 0 is located.
PCIe Block Location
Selects from the available integrated blocks to enable generation of location-specific constraint files and pinouts. This selection is used in the default example design scripts. This option is not available if a Xilinx Development Board is selected.
Lane Width
The core requires the selection of the initial lane width. The UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213) defines the available widths and associated generated core. Wider lane width cores can train down to smaller lane widths if attached to a smaller lane-width device. Options are 4, 8, or 16 lanes.
Maximum Link Speed
The core allows you to select the Maximum Link Speed supported by the device. The UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213) defines the lane widths and link speeds supported by the device. Higher link speed cores are capable of training to a lower link speed if connected to a lower link speed capable device. The default option is Gen3.
Reference Clock Frequency
The default is 100 MHz.
Reset Source
You can choose one of:
PCIe User Reset
The user reset comes from PCIe core after the link is established. When the PCIe link goes down, the user reset is asserted and the core goes to reset mode. And when the link comes back up, the user reset is deasserted.
Phy Ready
When selected, the core is not affected by PCIe link status.
AXI Data Width
Select 128, 256 bit, or 512 bit (only for UltraScale+). The core allows you to select the Interface Width, as defined in the UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213). The default interface width set in the Customize IP dialog box is the lowest possible interface width.
AXI Clock Frequency
250 MHz depending on the lane width/speed.
DMA Interface Option
You can select one of these options:
  • AXI Memory Mapped and AXI Stream with Completion
  • AXI Memory Mapped only
  • AXI Stream with Completion
Number of Queues (up to 2048)
Selects maximum number of queues. Options are 512 (default), 1024 and 2048.
Enable Bridge Slave Mode
Select to enable the AXI-MM Slave interface.
VDM Enable
Select to enable Vendor Define Messages.
AXI Lite Slave Interface
Select to enable the AXI4-Lite slave interface, which can access DMA queue space.
AXI Lite CSR Slave Interface
Select to enable the AXI4-Lite CSR slave interface, which can access DMA Configuration Space Register or Bridge registers.
Enable PIPE Simulation
When selected, this option enables an external third-party bus functional model (BFM) to connect to the PIPE interface of integrated block for PCIe. For details, see PIPE Mode Simulation Using Integrated Endpoint PCI Express Block in Gen3 x8 and Gen2 x8 Configurations (XAPP1184). Refer to these designs to connect the External PIPE Interface ports of the UltraScale™ device core to third-party BFMs.
Enable pipe simulation for faster simulation. This is used only for simulation.
Tandem Configuration or Dynamic Function eXchange
You can select the Dynamic Function eXchange (DFX) over PCIe, which uses the MCAP interface. Tandem Configuration modes are not supported for the QDMA Subsystem for PCIe.
Enable GT Channel DRP Ports
Enable GT-specific DRP ports.
Enable PCIe DRP Ports
Enable PCIe-specific DRP ports.
Additional Transceiver Control and Status Ports
Select to enable any additional ports.