Debug and Additional Options Tab - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

Document ID
Release Date
4.0 English

The Debug and Additional Options tab is shown below.

Figure 1. Debug and Additional Options Tab

Debug Options

Enable JTAG Debugging
This feature provides ease of debug for the following:
  • LTSSM state transitions:This shows all the LTSSM state transitions that have been made starting from link up.
  • PHY Reset FSM transitions: This shows the PHY reset FSM (internal state machine that is used by the PCIe solution IP).
  • Receiver Detect: This shows all the lanes that have completed Receiver Detect Successfully

For more details, see UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).

Enable In System IBERT
This debug option is used to check and see the eye diagram of the serial link at the desired link speed. For more information on In System IBERT, refer to In-System IBERT LogiCORE IP Product Guide (PG246).
Important: This option is used mainly for hardware debug purposes. Simulations are not supported when this option is used.
Add Mark Debug Utility
Adds predefined PCIe signals to with mark_debug attribute so these signals can be added in ILA for debug purpose.
Enable Descrambler for Gen3 Mode
This debug option integrates encrypted version of the descrambler module inside the PCIe core, which will be used to descrambler the PIPE data to/from PCIe integrated block in Gen3 link speed mode.
Enable PCIe Debug Ports
Reserved. This feature is not supported in this version.

Shared Logic Options

GT Wizard Options
You can select include GT Wizard in the example design and then the GT Wizard IP will be delivered into the example design area. You can reconfigure the IP for further testing purposes. By default, the GT Wizard IP will be delivered in the PCIe IP core as a hierarchical IP and you cannot re-customize it. For signal descriptions and for other details, see the UltraScale Architecture GTY Transceivers User Guide (UG578) or UltraScale Architecture GTH Transceivers User Guide (UG576).
This option is used to share the GT COMMON block used in the design when Gen2 (PLL Selection is QPLL1) and Gen3 link speeds are selected.
  • When Include GT COMMON in example design is selected, GT common block instance will be available in the support wrapper, which is inside the Xilinx top file and can be used either by the core or the external logic.
  • When Include GT COMMON inside GT Wizard is used, GT COMMON can be shared by external logic.
  • When No Sharing when inside GT Wizard and PCIe is selected, no sharing of GT COMMON block is allowed.
  • When Include GT COMMON in example design and Include GT Wizard in example design are selected together, you must use the latest GT COMMON settings from the example design project of the GT Wizard IP of the same configuration. This specific option delivers static GT COMMON wrappers which have the latest settings.

GT Settings

Form factor driven Insertion loss adjustment
Indicates the transmitter to receiver insertion loss at the Nyquist frequency depending on the form factor selection. Three options are provided:
  • Chip-to-Chip: The value is 5 dB
  • Add-in Card: The value is 15 dB and is the default option.
  • Backplane: The value is 20 dB.
These insertion loss values are applied to the GT Wizard subcore.
Link Partner TX Preset

It is not recommended that you change the default value of 4. However, a preset value of 5 might work better on some systems.

Disable GT Channel LOC Constraint
Reserved. Not supported in this version.