AXI Memory Mapped and AXI4-Stream With Completion Default Example Design - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

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4.0 English

The following is an example design generated when the DMA Interface Selection option is set to AXI Memory Mapped and AXI4-Stream with Completion option in the Basic tab.

Figure 1. Default Example Design

The generated example design provides blocks to interface with the AXI Memory Mapped and AXI4-Stream interfaces.

  • The AXI MM interface is connected to 512 KB of block RAM.
  • The AXI4-Stream interface is connected to custom data generator and data checker module.
  • The CMPT interface is connected to the Completion block generator.
  • The data generator and checker works only with predefined pattern, which is a 16-bit incremental pattern starting with 0. This data file is included in driver package.

The pattern generator and checker can be controlled using the registers found in the Example Design Registers. These registers can only be controlled through the AXI4-Lite Master interface. To test the QDMA Subsystem for PCIe's AXI4-Stream interface, ensure that the AXI4-Lite Master interface is present.