Clocking - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

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4.0 English
Figure 1. Clocking

PCIe® clocks (pipe_clk, core_clk, user_clk, and mcap_clk) are all driven by bufg_gt sourced from txoutclk pin. These clocks are derived clock from gtrefclk0 through a CPLL. In an application where QPLL is used, QPLL is only provided to the GT PCS/ PMA block while txoutclk continues to be derived from a CPLL. All user interface signals of the IP are timed with respect to the same clock (user_clk) which can have a frequency of 62.5, 125, or 250 MHz depending on the link speed and width configured. The QDMA Subsystem for PCIe and the user logic primarily work on user_clk.