In the platform-based design flow, the platform provides an expandable foundation for hardware development. The hardware design can be expanded through the use of PL kernels linked into the platform using the Vitis tools. PL kernels are hardware functions that can be generated from C++ in the Vitis HLS tool, or described directly in RTL in the Vivado Design Suite.
This section provides a brief overview of the Vitis development flow for PL kernels. A representation of this flow is shown below.
PL kernels can be written in C++ and synthesized into RTL IP using the Vitis HLS tool. As described in Vitis High-Level Synthesis User Guide (UG1399), there are fundamental concepts that need to be understood in order to design and write good synthesizable software in such a way that it can be successfully converted to hardware using high-level synthesis (HLS) tools.
PL kernels written in C++ can also be compiled directly into Xilinx object
files (.xo) using the v++ --compile command as described in Compiling C/C++ PL Kernels. However, the recommended method
for C/C++ kernels is to use a bottom-up methodology in Vitis HLS to let you perform analysis and optimization directly on the
kernel design to obtain the best results. In fact, the v++
--compile command uses Vitis HLS
as a key part of the compilation process.
PL kernels written in C++ can also be written in RTL, or may already exist
in catalogs of custom IP for use with the Vivado tools. As described in Packaging RTL Kernels, these
kernels have specific interface requirements to allow them to be linked into the
system design. Embedded system designers can also decide to integrate the RTL as
part of their custom platform, or link the RTL kernel into the system using the
v++ command as explained below.
Whether coming from Vitis HLS, RTL
kernel, or v++ --compile command, the results of
kernel development or compilation is a Xilinx object (.xo) file. The PL kernels have specific requirements regarding the
different types of supported interfaces, and clocks and reset signals as explained
in PL Kernel Properties. The clocks and resets let
XRT manage the execution of the kernels at run time, and the interfaces let the PL
kernels be linked with an extensible hardware platform (.xpfm) as well as with other .xo files, and AI Engine graph
applications (.libadf.a) as described in
Building and Packaging the System.