In the Vitis core development kit, targeted
devices can include AMD MPSoCs, AMD Kria™
SOMs, Versal
adaptive SoCs, or AMD UltraScale+™
FPGAs. The FPGA
contains a programmable region that implements and executes a device binary (.xclbin) file that contains and connects hardware kernels
as compiled Xilinx object (.xo) files and AI Engine graphs when appropriate.
The extensible FPGA platform contains one or more interfaces to global memory (DDR or HBM), and optional streaming interfaces (to other user-defined PL resources such as external I/Os).
PL kernels can access data through memory interfaces (m_axi) or streaming interfaces (axis). The memory interfaces of PL kernels must be connected to memory
interfaces of the extensible platform. The streaming interfaces of PL kernels can be
connected to any streaming interfaces of the platform, of other PL kernels, or of the AI
Engine array. Both memory-based and streaming connections are defined through Vitis linking options, as described in Linking the System.
Multiple kernels (.xo) can be implemented in the PL of the Xilinx device binary (.xclbin), allowing for significant application acceleration. A single kernel can also be instantiated multiple times. The number of instances of a kernel is programmable, and determined by linking options specified when building the FPGA binary.
For Versal AI Core devices the .xclbin file can also contain the AI Engine graph application (libadf.a). The libadf.a and PL kernels
(.xo) are linked with the target platform (.xpfm) to define the hardware design. The AI Engine can be driven by PL kernels through axis interfaces. The AI Engine can also be controlled through the Arm processor (PS) via run-time parameters (RTP) in the graph and GMIO on
Versal adaptive SoC devices. Refer to
AI
Engine Tools and Flows User Guide (UG1076) for more information.