Random Access and the RAMA IP - 2023.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)
Document ID
UG1393
Release Date
2023-07-17
Version
2023.1 English

HBM performs well in applications where sequential data access is required. However, for applications requiring random data access, performance can vary significantly depending on the application requirements (for example, the ratio of read and write operations, minimum transaction size, and size of the memory space being addressed). In these cases, the addition of the Random Access Memory Attachment (RAMA) IP to the target platform can significantly improve random memory access efficiency in cases where the required memory exceeds the 256 MB limit of a single HBM PC.

The RAMA IP will improve random access performance when 2 or more HBM PC are used. Refer to RAMA LogiCORE IP Product Guide (PG310) for more information.

Tip: To effectively use the RAMA IP in your application the kernel should access memory from multiple HBM PCs and should use a static single ID on the AXI transaction ID ports (AxID), or slowly changing (pseudo-static) AXI transaction IDs. If these conditions are not met, the thread creation used in the RAMA IP to improve performance has little effect, and consumes programmable logic resources for no purpose.

To use the RAMA IP add the keyword RAMA to the sp option in the config file, with the following format.

Note: The --connectivity.sp option requires the use of the <index> as described in the prior section.
sp=<compute_unit_name>.<argument>:<bank_name>.<index>.RAMA

For example: 

sp=krnl.out:HBM[3:4].3.RAMA