Creating and Packaging RTL Kernels - 2023.1 English

Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393)
Document ID
UG1393
Release Date
2023-07-17
Version
2023.1 English

Creating an RTL kernel begins with creating an IP within the Vivado Design Suite. You might have an existing RTL IP in your repository, or might want to create a new RTL design to package as an IP. Either approach is a good place to start in creating a new RTL kernel.

Execution Protocol

The RTL kernel employs a user-managed execution scheme where the host application generally uses register reads and writes to manage the execution and completion of the RTL kernel function. This user-managed execution protocol lets you use the control scheme of existing IP in the Vitis environment with little or no redesign, as explained in Creating User-Managed RTL Kernels. Typically this includes the use of an s_axilite interface and using XRT native API object classes and methods for reading and writing to register addresses on the kernel.

Port Interface Protocols

RTL kernels, like all kernels in the Vitis development flow, support four types of interfaces:
  • AXI4-Lite (S_AXILITE) for control registers, buffer pointers, scalar values, and kernel interactions with the host. The data is accessed by register reads and writes
  • AXI4 Memory Mapped (M_AXI) for access from the kernel to global memory or host memory. Data is accessed by the kernel through memory such as DDR, HBM, PLRAM/BRAM/URAM
  • AXI4-Stream ports to stream data between kernels, or other streaming sources such as a video processor or camera
  • Custom (non-AXI) interfaces are also supported using the --connectivity.connect command to make connection to these ports during the v++ linking process. This process can be used to connect your kernel to GT ports on the platform for instance

In addition, the kernels must have at least one clock, but can support multiple clocks, reset signals, and interrupts, as discussed in Kernel Interface Requirements. If your original IP does not use AXI4 interfaces, or provide the needed clock signal, you will need to modify and repackage the current IP to provide these signals.

A platform can have scalable clocks and fixed clocks. The Vitis flow can generate any number of derived fixed clocks that are not provided by the platform and are commonly used for RTL kernel flow. When fixed clocks are used, Vitis flow will insert an MMCM into the system design to generate the required frequencies. Refer to Managing Clock Frequencies for more information.

The data bus width of the AXI master and stream ports are configurable. Normally this depends on data transfer bandwidth and FPGA resource considerations.

The design of the RTL kernel is highly flexible. You can decide the interaction method between the kernel and the host application, the internal clock generation scheme, clock gating strategy, handling of interrupts.

Tip: You might need to use the AXI Clock Converter as part of the AXI Interconnect Core IP to manage cross-domain clocking from outside the kernel to inside. It might be hard to achieve timing closure if you treat the external bus clock and internal bus clock as synchronous.

Packaging the IP

To generate the RTL kernel you must run the Package IP process in the Vivado tool, as described in Packaging the RTL Code as a Vitis XO. This is the standard IP packaging flow as described in Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118), with the additional step of specifying the kernel for use in the Vitis design flow.