In the AMD Vitis™ core development kit, the PL kernel code is generally a compute-intensive part of the system, and intended to run on the programmable logic (PL) region of an AMD device. The Vitis core development kit supports PL kernel code written in C or C++, and also written in RTL. For C/C++ based kernels the Vitis HLS tool offers the best place to start.
The Vitis HLS tool, which is part of the Vitis core development kit, is targeted at the development of PL kernels written in C or C++. The environment provides a language sensitive editor, simulation and code analysis tools, high-level synthesis of RTL from the C or C++ code, and C-RTL co-simulation for an in-depth examination of the resulting hardware design. Vitis HLS is the recommended tool for developing PL kernels for use in the AMD Vivado™ traditional design flow, or in the Vitis heterogeneous design flow.
Generally, off-the-shelf software cannot be efficiently converted into hardware running on an FPGA. Even if the software program can be automatically converted (or synthesized) into hardware, achieving acceptable quality of results (QoR) will require additional work such as structuring the algorithm to help Vitis HLS achieve the desired performance goals. To help, you need to understand the best practices for writing good software for execution on the FPGA as discussed in Design Principles in the Vitis HLS User Guide (UG1399).
The code for C++ kernels written and optimized in Vitis HLS can be compiled in the Vitis tools either from the v++
command line as explained in Compiling C/C++ PL Kernels, or from an Application project in the
Vitis IDE as explained in Creating a Vitis IDE Project.
extern "C"
linkage
in the header file, or the whole function in the kernel source code must be
wrapped.extern "C" {
void kernel_function(int *in, int *out, int size);
}