Support for hardware accelerator pipelines that communicate through streams is
one of the major advantages of FPGAs, FPGA-based SoCs, and Versal adaptive SoC devices, and have been used in DSP and image
processing applications, as well as in communication systems. Kernel ports involved in
streaming are defined within the kernel, and are not addressed by the host program.
There is no need to send data back to global memory before it is forwarded to another
kernel for processing. The connections between the kernels are directly defined during
the v++
linking process as described below.
A streaming data output port of one kernel can be connected to the
streaming data input port of another kernel, or between a PL kernel and the PLIO of an
ADF graph application, during linking using the --connectivity.sc
option. This option can be specified at the command
line, or from a config
file that is specified using
the --config
option, as described in v++ Command.
--connectivity.sc
kernel drives itself.To connect the streaming output port of a producer kernel to the streaming
input port of a consumer kernel, set up the connection in the v++
config file using the connectivity.stream_connect
option as follows:
[connectivity]
#stream_connect=<cu_name>.<output_port>:<cu_name>.<input_port>:[<fifo_depth>]
stream_connect=vadd_1.stream_out:vadd_2.stream_in
stream_connect=vadd_2.stream_in:ai_engine_0.DataIn0
Where:
-
<cu_name>
is an instance name of the CU as determined by theconnectivity.nk
option, described in Creating Multiple Instances of a Kernel. Note that thecu_name
can be specified in the config file as described in Creating Multiple Instances of a Kernel, or is defined automatically by the tool when not otherwise specified.Tip: When specifying connections to Versal AI Engine ports, the<cu_name>
will beai_engine_0
as shown above. -
<output_port>
or<input_port>
is the streaming port defined in the producer or consumer kernel.Important: If the port-width of the output and input ports do not match, the Vitis compiler will automatically insert a data-width converter between the two ports as part of the build process. The inclusion of the data-width converter will either truncate a larger bit-width output to a smaller bit-width input, or expand a smaller bit-width to a larger bit-width. -
[:<fifo_depth>]
inserts a FIFO of the specified depth between the two streaming ports to prevent stalls. The value is specified as an integer.