Vitis Export Flow Guidelines and Limitations - 2023.1 English

In the 2023.1 release, only single SLR AMD Versal™ devices are supported with the AMD Vitis™ Export to Vivado Flow. The Vitis Export flow does not support hardware emulation (-t=hw_emu).

The v++ compiler operates on a Vivado project that has been encapsulated in an extensible XSA built in Vivado. Conversely, the block design of the VMA is imported into a project as a design source that the user can continue to modify in Vivado.

In general, any modification to the Vivado project after vitis::import_archive that does not invalidate the contract between the imported design and the .xclbin metadata contained within the VMA is supported. The following table enumerates supported and prohibited operations.

Supported operations include:

• Adding, removing, and reconfiguring IPs and RTL modules outside of and unconnected to the Vitis region hierarchy within the dynamic region block design.
• Add, removing, or changing connections unconnected to the Vitis region hierarchy within the dynamic region block design.
• Changing clock frequencies on clock wizard instances outside of the Vitis region hierarchy within the dynamic region block design.
• Changing QoS settings on axi_noc instances in the dynamic region block design.
• Adding .xdc constraints associated with any part of the design, including within the Vitis region hierarchy within the dynamic region block design.

Prohibited operations include:

• Adding or deleting any IP instances or connections within the Vitis region hierarchy within the dynamic region block design.
• Adding or deleting connections between the dynamic region and the Vitis region hierarchy.
• Changes to the address map that modifies any address APERTURES or IP addressing in the Vitis region hierarchy within the dynamic region block design.
• Project changes that modify the netlist path to the Vitis region hierarchy within the dynamic region block design.

Current limitations of the Vitis Export flow include the following:

• The Vivado dynamic region block design must be a block design container, and as a result, some base platforms, e.g., vck190_base, currently do not support the flow.
• Supported for Versal platforms only.