This section explains the Vitis Export flow as shown in the following diagram. The complete flow (from hardware design creation to export .xclbin) is divided into seven steps.
You can execute the flow in the following steps:
-
Start by creating the Versal custom platform design. The Vitis export flow requires block-design container (BDC) designs as described in Generate XSA file, and does not support flat designs. You can use HLS-based components, or RTL-based packaged IP, or standard IP from the IP catalog in your Vivado design.
After creating the platform, run synthesis to clean any issues related to hardware realization. Only use the flow for the Versal device platforms. Export the platform into
extensible.xsa
using following steps:-
Click on Export Platform under IP Integrator in the Flow Navigator.
In Export Platform, select the Presynthesis option to generate the extensible.xsa.
Tip: If the Export Platform option is disabled, go to Project Settings and select Project is an extensible Vitis Platform.
- From the Tcl console, enter the command
write_hw_platform -f <filename>.xsa
-
-
In the Vitis tool, the exported .xsa becomes the platform of choice, and the system design is completed.
- Compile the AI Engine graph (libadf.a)
- Compile PL kernels (.xo)
- Update system.cfg file for connectivity
- Run
v++
linker with--export_archive
option
In the Vitis Export to Vivado flow the system linking process occurs as usual, but the automatic launch of Vivado synthesis and place and route is skipped. Instead the
v++ --link --export_archive
command is used to generate the Vitis metadata archive (.vma) to export to the Vivado Design Suite.Note:--export_archive
cannot be used with the--target
.v++ --link --platform ../<>.xsa --config ../system.cfg ./<libadf.a> ./<.xo> --export_archive -o <vma_file>.vma
- Open the Vivado project
after generating the .vma file from the
Vitis tools. Import the .vma file in the Vivado project, or new project, with the following Tcl procedure:
vitis::import_archive ./vma_path/<vma_file>.vma
- A new variant for the dynamic region block design container will be created by cloning the VMA's block design and made active.
- Within the dynamic region block design, Vitis content is encapsulated within a level of hierarchy that the user should consider essentially read-only whenever they intend to use XRT after implementing the design in Vivado. See the Vitis Export Flow Guidelines and Limitations section for more details on how to preserve XRT metadata consistency while updating the design in Vivado.
- The .vma region
can be opened in Vivado.
Alternatively, to rerun Vitis
flows, you can re-export an extensible XSA after removing Vitis content via
vitis::remove_archive_hierarchy
.
- After importing the .vma
to the Vivado tools, design modifications
can be done in Vivado only. See the Vitis Export Flow Guidelines and Limitations section for more
information.
- If there are changes to the
.vma
file, such as changes to the AI Engine design, PL kernels, or to the PLIO boundary, go to Step 5 to regenerate the .xsa file and reiterate through the Vitis Export to Vivado flow. - If the design changes are related to Vivado only, then simulate the design, synthesize and implement the design to meet timing, and then go to Step 6 for generating the fixed.xsa.
- If there are changes to the
- If the design requires changes related to the AI Engine, PL kernels,
or updates in the PLIO boundary, these changes require updates to the linked
system design, and regenerating the .vma
in the Vitis tool. Thus, you must first
remove the previously imported .vma from
the Vivado project using one of two Tcl
procedures:
- Use the
vitis::remove_archive_hierarchy
procedure to remove the imported .vma file while preserving any work done to the Vivado project after importing the .vma. - Use the
vitis::remove_archive
procedure to restore the Vivado project to its state prior to importing the .vma file, removing both the .vma and any changes to the project.
After removing .vma from the Vivado design, you can make any changes to the project. Vitis depends only upon the dynamic region block design and to potential connectivity points declared through PFM APIs. Update
system.cfg
to update the boundary connections. If there is a need to export the extensible.xsa for the second iteration or later from Vivado, use thevitis::remove_archive
command and repeat Step 1 to export theextensible.vma
; repeat Step 2 and 3 to export the VMA from Vitis and import VMA to Vivado respectively. - Use the
-
Once you have implemented your design, you can generate a fixed.xsa from the Vivado project by using the following command:
write_hw_platform -fixed ./<fixed_xsa>.xsa
This XSA can be used to perform the application development for PetaLinux / Yocto or XRT-based apps development, PS-based apps development through Vitis embedded software flow, or baremetal flow as it has been done traditionally.
- When you are ready to run the design on the hardware target, run
v++ --package
to generate the.xclbin