Reduce the Number of Partition Pins - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2021.1 English

All reconfigurable module (RM) pins must have a partition pin location constraint (PPLOC) deposited by the placer. The only exception is dedicated paths between hard primitives. The partition pin is the physical interface on fabric that separates the static and reconfigurable portions of a boundary signal.

The presence of partition pins reduces the solution space for the router, because the related boundary net is always forced to route through the partition pin. To alleviate this issue, the DFX flow includes expanded routing. Expanded routing is the additional routing footprint for a reconfigurable partition (RP) that can include routing tiles from the static region. When the static Endpoint of a boundary net is placed in the expanded routing footprint of an RP, PPLOC reduction occurs in the router for that boundary signal. This allows the router to reroute the boundary net from a static Endpoint to an RM Endpoint during subsequent child implementations, instead of locking boundary nets down to a PPLOC. Xilinx recommends expanded routing to reduce the dependency of the router on PPLOCs.

In the following example, the static region is not in the expanded routing footprint of the RP. PPLOC reduction is not triggered, and there is a large number of PPLOCs in the reconfigurable Pblock after route_design.

Figure 1. Static Endpoint Outside Expanded Routing Footprint of RP

In the following example, the Static Endpoints to the RP Pblock are assigned to a thin static Pblock, which is defined in the expanded routing footprint of the RP Pblock. There are no PPLOCs remaining after route_design.

Figure 2. Static Endpoints to the RP Pblock Assigned to the Static Pblock

For more information on PPLOCs, see this link, and for more information on expanded routing, see this link in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).