Using Vitis HLS in the Vitis Kernel Flow - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2021.1 English

When targeting Versal devices, the platform-based design flow allows programming most of the device using the C++ language:

  • The software application running on the PS can be written in C/C++
  • The AI Engine graph is written in C/C++
  • PL kernels can be written in C/C++ and compiled to hardware using the Vitis HLS tool
Recommended: Xilinx recommends using Vitis HLS and the Vitis kernel flow for PL blocks, which tightly interact with an AI Engine graph. Using the same high-level language to model as much of the system as possible allows for easier collaboration between teams, simpler exchange of information, faster iterations, and quicker simulations.