Creating a Design with GT IP - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
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2021.1 English

For Versal ACAP, GT components are updated from Common/Channel to a GT Quad granularity. To enable some of the GT sharing use cases, GT wizard flows use the Vivado IP integrator. You can use the Vivado IP integrator to build system designs using single or multiple GT Quads.

The Versal ACAP GTY Transceivers Wizard IP solution helps configure one or more serial transceivers. The Transceivers Wizard solution contains the following cores:

Transceivers Bridge
A reference parent IP (Bridge IP) that configures Transceivers Wizard.
Transceivers Wizard
A wrapper around the GTYE5_QUAD primitive. It consists of single GT Quad (GT quad base IP). Multiple Transceivers Wizards are instantiated for multi-lane (greater than 4 lanes) designs.
Note: The GT Wizard does not add physical locations for GT Quads. Instead, the I/O Planner is used to add GT I/O and GT reference clock pin locations.