SelectIO I/O Logic Clocking - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2021.1 English

The Versal device SelectIO I/O logic primitives have maximum skew requirements between clock pins. Using the optimal clocking topology for the SelectIO I/O logic primitives prevents maximum skew violations, improves interface timing between the Versal device and the fabric logic, and uses fewer clocking resources.