Xilinx strongly recommends creating PL kernels with the following interfaces:
- At least one clock and one reset
- Standard AXI interfaces:
- Memory mapped AXI4 interface for memory mapped transfers over the NoC
- AXI4-Stream for connections to other PL kernels, AI Engine graphs, or streaming platform ports
- AXI4-Lite for control by the PS (software controllable kernels only)
For more information, see HW Interfaces in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).
Working with standard AXI interfaces enables design automation by the Vitis tools flow and reduces manual and error-prone
tasks. However, it is also possible for PL kernels to have non-AXI interfaces. In this
case, you need to manually and explicitly connect each of the non-AXI signals during the
Vitis linking phase using the connectivity.connect option, as described in
--connectivity.connect
in the Application Acceleration Development flow of the Vitis Unified Software Platform
Documentation (UG1416).