PL kernels can connect and interact with AI Engine graphs using streaming interfaces. These streaming interfaces are implemented using the AXI4-Stream protocol.
Vitis HLS provides the hls::stream<> C++ class library to facilitate the
modeling and synthesis of designs with streaming interfaces. In the Vitis kernel flow, Vitis HLS automatically infers AXI4-Stream interfaces from C++ code using the hls::stream<> class. For more information on this library, see
HLS Stream Library in the Vitis HLS flow
of the Vitis Unified Software Platform
Documentation (UG1416).
In addition to the simple transfer of data, the AXI4-Stream protocol provides optional sideband signals
to convey additional control information. The AXI4-Stream sideband signals can be modeled using the hls::axis<> data type. For more information, see
Managing Interface
Synthesis in the Vitis HLS flow of the Vitis Unified Software Platform
Documentation (UG1416).