The IP integrator uses a variety of sources, including the Xilinx® IP catalog, other block designs, custom packaged IP, and referenced RTL modules. The sources must be used correctly to simplify the design structure and improve individual and team productivity. The following table summarizes key advantages and disadvantages associated with different sources.
| IP | Block Design | RTL | |||
|---|---|---|---|---|---|
| Catalog IP | Custom Packaged IP | Packaged Block Design | Block Design Container | RTL Module Reference | |
| Team Design Benefit | High | High | Low | High | Medium |
| Design Advantage | Standard method for building a block design | Converts HDL modules into reusable IP blocks | Converts BD into reusable custom packaged IP | Allows instantiation of a BD within another BD | Allows HDL portions of the design to be added to a BD |
| Key Advantages | Tested and verified IP blocks |
|
Ability to integrate legacy BDs into newer designs Note: BDCs are recommended instead of this approach.
|
|
Quick way to add RTL without IP packaging effort |
| Key Limitations | Customization limited to available IP settings without option to modify IP sources | Inability to view or modify from top BD | Packaged BD contains fixed addressing information | Nested BD not yet supported | Design checkpoint and nested BD not allowed in the RTL files |
The following sections highlight methodologies that best leverage these sources and IP integrator capabilities to improve the structure and integration of complex Versal ACAP designs.