Design Creation with RTL - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2021.1 English

Xilinx requires the use of the Vivado® IP integrator to instantiate and configure the CIPS and NoC IP for Versal™ devices. The platform management controller (PMC) is contained within the CIPS IP and is required to boot and configure all Versal devices. The CIPS IP is only available in IP integrator.

Although not required, Xilinx recommends using the IP integrator to create the top-level RTL wrapper for your design. Enabling the Vivado tools to maintain the RTL wrapper simplifies the simulation of the design, because the Vivado tools can to automatically connect proper simulation models for the NoC IP. It is possible to configure the CIPS and NoC in the IP integrator, specify all external interfaces to the rest of the design, and instantiate the resulting block design in the top-level RTL. This approach contains the CIPS and NoC to a subset of the larger system but requires that you manually ensure the proper simulation models are connected correctly in their RTL wrappers.