High Fanout Clocks - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
Release Date
2021.1 English

A high fanout clock spans almost all clock regions of a Versal device. The following figure shows a high fanout clock that spans almost an entire Versal device with the XPIO bank BUFGCE driver shown in red.

Figure 1. High Fanout Clock Spanning an Entire Versal ACAP
Note: Using more than 24 high fanout clocks in a design might cause issues that require special design considerations or other upfront planning.