AMBA AXI - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
Release Date
2021.1 English

Xilinx has standardized IP interfaces on the open AMBA® 4 AXI4 interconnect protocol. This standardization eases integration of IP from Xilinx and third-party providers, and maximizes system performance. Xilinx has worked with Arm® to define the AXI4, AXI4-Lite, and AXI4-Stream specifications for efficient mapping into its device architectures.

AXI4 is targeted at high performance, high clock frequency system designs, and is suitable for high-speed interconnects. AXI4-Lite is a light-weight version of AXI4, and is used mostly for accessing control and status registers.

AXI4-Stream is used for unidirectional streaming of data from Master to Slave. This is typically used for DSP, Video and Communications applications.