Avoid RP to RP Direct Paths - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2021.1 English

Xilinx recommends avoiding direct timing paths between multiple reconfigurable partitions (RPs) for the following reasons:

  • If the boundary signal between the RPs does not have a static Endpoint, the DFX flow must deposit a PPLOC on both RPs. As a result, tool capabilities like expanded routing with PPLOC reduction cannot be used. The presence of these PPLOCs also causes routability challenges in child implementations.
  • If the timing paths across an RP do not have a static Endpoint, there might be a combination of reconfigurable modules (RMs) in two RPs that do not meet timing. The omission of a synchronous timing point in the static portion of the design can also lead to timing and hardware failures depending on the RMs that are currently loaded. The HDPR-34 and HDPR-35 DRCs flag this issue.