Designing Efficient Kernels - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2021.1 English

Using C/C++ to model and create hardware offers coding flexibility. For maximum predictability and a faster path to results, Xilinx recommends the load-compute-store coding style where the kernel is explicitly decomposed between data motion blocks and computational blocks. This highly structured coding style fits the producer-consumer pattern well and helps achieve high-throughput designs. For more information, see Designing Efficient Kernels in the Vitis HLS flow of the Vitis Unified Software Platform Documentation (UG1416).