USER_CLOCK_ROOT Assignment - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
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2021.1 English

USER_CLOCK_ROOT assignment in Versal ACAP differs slightly from UltraScale devices due to changes in the clocking architecture. In Versal ACAP, not all clock regions have a vertical clock spine, and these clock regions cannot be used for USER_CLOCK_ROOT assignment.

The following figure shows the locations of the vertical clock spines. The clock spines highlighted in yellow are adjacent to the vertical NoC column at the boundary of two clock regions. The Vivado tools only allow the USER_CLOCK_ROOT to be set to the left clock region of these clock spines. The clock regions highlighted in green indicate the load locations of the clkOut_div8 clock net.

The vertical clock spines in the transceiver Quad columns on the left and right side of the device are highlighted in light blue. A USER_CLOCK_ROOT can be assigned to any clock region in those columns. However, assigning a USER_CLOCK_ROOT to a clock region in the leftmost transceiver Quad column, above the PS, blocks the clock from reaching any loads to the right of the PS.

Figure 1. Vertical Clock Spines and Clock Regions of clkOutdiv8 Loads

In the following example, the USER_CLOCK_ROOT constraint is illegal, because the constraint is set to the clock region to the right of the vertical clock spine:

set_property USER_CLOCK_ROOT X4Y3 [get_nets -of [get_pins BUFGCE_DIV_div8_inst/O]]

In this case, the placer issues a message and assigns a legal CLOCK_ROOT to the net in CLOCK_REGION X3Y3.

Important: For complete control of your placement and USER_CLOCK_ROOT selection, Xilinx recommends that you create a Pblock that contains all of the loads of your clock network. Then, assign the USER_CLOCK_ROOT to a clock region that contains the vertical clock spine. In most cases, the Vivado placer selects the optimal CLOCK_ROOT for your design, and the manual USER_CLOCK_ROOT assignment is not necessary.