Using the GCLK_DESKEW Property on a Clock Net - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2021.1 English

You can use the GCLK_DESKEW property to disable calibrated deskew for a clock net. Calibrated deskew is enabled by default for all Versal device clocks and calibrates the initial delay taps for a clock network at device startup to further minimize clock skew. For some clocking topologies, it is more important to minimize insertion delay, and clock network deskew is of lesser importance for timing closure. In these cases, you can implement a clock network without additional delays to balance clock skew by setting the GCLK_DESKEW property on a clock net to OFF. This also disables calibrated deskew for the clock net. You must set the GCLK_DESKEW property on the net segment directly driven by the clock buffer. Following is an example:

set_property GCLK_DESKEW OFF [get_nets -of [get_pins clkgen/BUFG_clkout2_inst/O]]
Note: The GCLK_DESKEW property works best when used with a USER_CLOCK_ROOT constraint to force the clock root closer to the loads that require the least insertion delay.