Creating a Design with IP for PCIe Subsystems - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2021-07-26
Version
2021.1 English

The Versal architecture uses two different types of integrated blocks to enable PCIe interface designs. Versal devices can contain one or more instances of a PL-integrated block for PCIe interface designs. Versal devices can also contain one CPM, which resides adjacent to the PS. Multiple versions of both these integrated blocks exist in the Versal architecture. You can configure the Versal ACAP integrated block for PCI Express® interfaces can by double-clicking the selected IP within the IP catalog. The CPM configuration must be configured within the CIPS IP block. For more information, see the following documents:

  • Versal ACAP CPM CCIX Architecture Manual (AM016)
  • Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)
  • Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
  • Versal ACAP PCIe PHY LogiCORE IP Product Guide (PG345)
  • Versal ACAP CPM Mode for PCI Express Product Guide (PG346)
  • Versal ACAP CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)