Revision History - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
Release Date
2021.1 English

The following table shows the revision history for this document.

Section Revision Summary
07/26/2021 Version 2021.1
System Design Types Revised traditional and platform-based design flows summary.
Design Planning Added new chapter.
Design Creation with Block Designs Updated introduction.
Creating a Block Design with IP Integrator Added new sections.
Creating a Design with CIPS IP Added information on automation.
NoC IP DDR4 Memory Controllers Added new section.
Creating a Platform for the Platform-Based Design Flow Added new section.
Design Creation with RTL Updated IP integrator requirement.
Auto-Pipelining Considerations Added new section.
Coding for FIFOs Added new section.
Coding Recommendations for Creating and Packaging RTL Kernels for the Platform-Based Design Flow Added new section.
Clock Routing, Root, and Distribution Added example and updated figure.
Clock Tree Placement and Routing Clarified physical optimizer and clock network interaction.
Using the GCLK_DESKEW Property on a Clock Net Added new section.
Gating the Clock Buffer Added note about MMCME5 feedback path.
Clocking Recommendations for Platforms and Dynamic Function eXchange Added new section.
Vitis HLS Methodology Added new sections.
Design Constraints Added note about traditional and platform-based design flows.
Constraining Input and Output Ports Added note about I/O logic.
Defining Power and Thermal Constraints Added new section.
Floorplanning Constraints for Dynamic Function eXchange Added new section.
Specifying the RAM Activity for Jitter Added new section.
Running Synthesis Added note about IP integrator.
NoC Compiler Runs During Placement Added new section.
Creating the Device Image Added information on DRC and DFX considerations.