Interfacing HLS Kernels to the NoC - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2021.1 English

PL kernels can connect and interact with the Versal NoC using memory mapped interfaces. These memory mapped interfaces are implemented using the memory mapped AXI4 protocol.

In the Vitis kernel flow, Vitis HLS automatically infers memory mapped AXI4 interfaces from the pointer arguments of the top-level function. However, for high-performance designs, the developer must ensure that these interfaces are efficiently accessed. In particular, making single accesses at random memory locations is inefficient. It is important for the kernel to perform sequences of accesses in contiguous memory locations from which bursting transactions can be inferred. For more information, see Managing Interface Synthesis in the Vitis HLS flow of the Vitis Unified Software Platform Documentation (UG1416) and Optimizing Burst Transfers in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).