NoC Compiler Runs During Placement - 2021.1 English

Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387)

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2021.1 English

The Vivado IP integrator invokes the NoC Compiler during block design validation to generate a NoC placement and routing solution to meet QoS requirements. If the solution from IP integrator does not sufficiently meet design implementation requirements, the NoC Compiler might be invoked during design placement to generate a new solution to meet the implementation requirements.

Figure 1. NoC Compiler Flow

The following are implementation requirements that might cause the NoC Compiler to be invoked during design placement:

  • Physical location or Pblock constraints applied to the PL that will influence NoC NMU/NSU placement
  • Resolution of the NoC interface between CIPS and NoC for proper assignment to the targeted device
  • Top-level port assignment of DDRMC interfaces that will result in a change in DDRMC assignment
Tip: In the IP integrator, you can constrain the location of the DDRMC to the appropriate site in the NoC View to reflect the assignment to perform during design placement. This improves the NoC QoS results correlation between IP integrator and a fully implemented design.