Step Load Assumptions

Different step loads are assumed for each main voltage rail. The step load is the percentage of the dynamic current that is expected to be demanded at any given switching event. Table: Step Load for Device Capacitance lists the step load percentage used when calculating device capacitance requirements.

The slew rate of the switching event is dependent on the design, and can be estimated to be between 1 ns and 100 ns (or longer). Smaller current designs generally have faster current slew rates, while larger designs tend to have slower slew rates. A general rule of thumb for high-current designs can be considered to be 0.25 ns per amp (or 4 A/ns) of step current.

The Xilinx Power Estimator (XPE) tool is used to estimate the current on each power rail. Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) [Ref 1] and Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893) [Ref 2] provide the operating range for all the various power rails. The PCB designer should ensure that the AC ripple plus the DC tolerance of the voltage regulator do not exceed the operating range.

The capacitor numbers shown in this user guide are based on the following assumptions:

V_CCINT operating range from the data sheet = 3%;

Assumed DC tolerance = 1%;

Therefore, allowable AC ripple = 3% – 1% = 2%.

The target impedance is calculated using the 2% AC ripple along with the current estimates from XPE for the above resource utilization to arrive at the capacitor recommendations. The equation for target impedance is:

Equation 1-1      

V_CCINT, V_CCAUX, and V_CCBRAM capacitors are listed as the quantity per device, while V_CCO capacitors are listed as the quantity per I/O bank. Device performance at full utilization is equivalent across all devices when using these recommended networks.

The decoupling capacitor tables in Appendix A do not provide the decoupling networks required for the GTY or GTH transceiver power supplies. For this information, refer to the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 6] or the UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 7].

 

RECOMMENDED:   Refer to the UltraScale Architecture Schematic Review Checklist (XTP344) [Ref 8] and UltraScale+ FPGA and Zynq UltraScale+ MPSoC Schematic Review Checklist (XTP427) [Ref 18] for a comprehensive checklist for schematic review which complements this user guide.

Note:   The capacitor values and part numbers have been updated taking into account the latest product offerings from various vendors because some of the part numbers from the previous versions of this user guide have reached end of life. The new guidelines also incorporate capacitors with a wider temperature range (X6S) compared to the previous part numbers, while moving away from a combination of tantalum/ceramic capacitors to solely ceramic capacitors across the entire frequency range. The prior capacitor tables and specifications are still valid for existing designs, but for new designs, the current tables and specifications are recommended.